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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADV7192 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 2000 video encoder with six 10-bit dacs, 54 mhz oversampling and progressive scan inputs features six high-quality 10-bit video dacs 10-bit internal digital video processing multistandard video input multistandard video output 4 oversampling with internal 54 mhz pll programmable video control includes: digital noise reduction gamma correction black burst luma delay chroma delay multiple luma and chroma filters luma ssaf (super subalias filter) average brightness detection field counter macrovision rev. 7.1 cgms (copy generation management system) wss (wide screen signaling) closed captioning support. teletext insertion port (pal-wst) 2-wire serial mpu interface (i 2 c -compatible and fast i 2 c) i 2 c interface supply voltage 5 v and 3.3 v operation 80-lead lqfp package ssaf is a trademark of analog devices inc. this device is protected by u.s. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). i 2 c is a registered trademark of philips corporation. throughout the document yuv refers to digital or analog component video. applications dvd playback systems pc video/multimedia playback systems progressive scan playback systems general description the ADV7192 is part of the new generation of video encoders from analog devices. the device builds on the performance of previous video encoders and provides new features like interfac- ing progressive scan devices, digital noise reduction, gamma correction, 4 oversampling and 54 mhz operation, average brightness detection, black burst signal generation, chroma delay, an additional chroma filter, and other features. the ADV7192 supports ntsc-m, ntsc-n (japan), pal n, pal m, pal-b/d/g/h/i and pal-60 standards. input stan dards supported include itu-r.bt656 4:2:2 ycrcb in 8-bit or 16-bit format and 3 10-bit ycrcb progressive scan format. the ADV7192 can output composite video (cvbs), s-video (y/c), component yuv or rgb and analog progressive scan in yprpb format. the analog component output is also compatible with betacam, mii, and smpte/ebu n10 levels, smpte 170 m ntsc, and ituCr.bt 470 pal. please see detailed description of features for more informa- tion about the ADV7192. simplified functional block diagram i 2 c interface chroma lpf 10-bit dac 10-bit dac 10-bit dac 10-bit dac 10-bit dac 10-bit dac 2 oversampling 4 oversampling or ADV7192 ssaf lpf luma lpf composite video y [s-video] c [s-video] rgb yuv yprpb tv screen or progressive scan display color control dnr gamma correction vbi teletext closed caption cgms/wss demux and ycrcb- to- yuv matrix pll and 54mhz video input processing video output processing video signal processing analog output 27mhz clock ituCr.bt 656/601 8-bit ycrcb in 4:2:2 format digital input
ADV7192 ? rev. 0 contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 simplified functional block diagram . . . . . . 1 specifications static performance 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 static performance 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . 4 dynamic speci?cations 5 v . . . . . . . . . . . . . . . . . . . . . . . . 5 dynamic speci?cations 3.3 v . . . . . . . . . . . . . . . . . . . . . . . 5 timing characteristics 5 v . . . . . . . . . . . . . . . . . . . . . . . . 6 timing characteristics 3.3 v . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . 9 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 package thermal performance . . . . . . . . . . . . . 9 pin function descriptions . . . . . . . . . . . . . . . . . 10 detailed description of features . . . . . . . . . 11 general description . . . . . . . . . . . . . . . . . . . . . . . . 11 data path description . . . . . . . . . . . . . . . . . . . . . 12 internal filter response . . . . . . . . . . . . . . . . . . . 13 features: functional description . . . . . . . . . 17 black burst output . . . . . . . . . . . . . . . . . . . . . . . . 17 brightness detect . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chroma/luma delay . . . . . . . . . . . . . . . . . . . . . . . . 17 clamp output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 cso , hso and vso outputs . . . . . . . . . . . . . . . . . . . 17 color bar generation . . . . . . . . . . . . . . . . . . . . . . 17 color burst signal control . . . . . . . . . . . . . . . 17 color controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chrominance control . . . . . . . . . . . . . . . . . . . . . 17 undershoot limiter . . . . . . . . . . . . . . . . . . . . . . . . 18 digital noise reduction . . . . . . . . . . . . . . . . . . . . 18 double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 gamma correction control . . . . . . . . . . . . . . . 18 ntsc pedestal control . . . . . . . . . . . . . . . . . . . . . 18 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 progressive scan input . . . . . . . . . . . . . . . . . . . . . 18 real-time control, subcarrier reset, and timing reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 sch phase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 square pixel mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vertical blanking data insertion and blank input . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 yuv levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 oversampling and internal pll . . . . . . . . . 20 video timing description . . . . . . . . . . . . . . . . . . . 20 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mpu port description . . . . . . . . . . . . . . . . . . . . . . . 28 register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 register programming . . . . . . . . . . . . . . . . . . . . . 29 mode registers 0C9 . . . . . . . . . . . . . . . . . . . . . . . 30C35 timing registers 0C17 . . . . . . . . . . . . . . . . . . . . . . . 36 subcarrier frequency and phase registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 closed captioning registers . . . . . . . . . . . . . . . 37 ntsc pedestal/pal teletext control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 teletext control register . . . . . . . . . . . . . . . . 38 cgms_wss registers . . . . . . . . . . . . . . . . . . . . . . . . . 38 contrast control registers . . . . . . . . . . . . . . . 39 hue adjust control register (hcr) . . . . . . . . 40 hcr bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40 brightness control register (bcr) . . . . . . . . 40 bcr bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40 sharpness response register (pr) . . . . . . . . . . . 41 pr bit description . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dnr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 dnr bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 41 gamma correction registers . . . . . . . . . . . . . . 43 brightness detect register . . . . . . . . . . . . . . . . 44 output clock register . . . . . . . . . . . . . . . . . . . . . 44 ocr bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . 44 appendix 1 board design and layout considerations . . . . . . . . . . . . 45 appendix 2 closed captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 appendix 3 copy generation management system (cgms) . . . . . . . 48 appendix 4 wide screen signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 appendix 5 teletext insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 appendix 6 optional output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 appendix 7 dac buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 appendix 8 recommended register values . . . . . . . . . . . . . . . . . . . . 53 appendix 9 ntsc waveforms (with pedestal) . . . . . . . . . . . . . . . . . 57 ntsc waveforms (without pedestal) . . . . . . . . . . . . . . . 58 pal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 video measurement plots . . . . . . . . . . . . . . . . . . . . . . . . 60 uv waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 appendix 10 vector plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 69
? rev. 0 ADV7192 5 v specifications 1 parameter min typ max unit test conditions static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 3 1.0 lsb differential nonlinearity 3 1.0 lsb guaranteed monotonic digital inputs input high voltage, v inh 2.0 v input low voltage, v inl 0.8 v input current, i in 0 1 av in = 0.4 v or 2.4 v input capacitance, c in 610 pf input leakage current 4 1 a input leakage current 5 200 a digital outputs output high voltage, v oh 2.4 v i source = 400 a output low voltage, v ol 0.8 0.4 v i sink = 3.2 ma three-state leakage current 6 10 a three-state leakage current 7 200 a three-state output capacitance 6 10 pf analog outputs output current (max) 4.125 4.33 4.625 ma r l = 300 ? output current (min) 2.16 ma r l = 600 ? r set1, r set2 = 2400 ? dac-to-dac matching 3 0.4 2.5 % output compliance, v oc 0 1.4 v output impedance, r out 100 k ? output capacitance, c out 6pfi out = 0 ma voltage reference reference range, v ref 8 1.112 1.235 1.359 v power requirements v aa 4.75 5.0 5.25 v normal power mode i dac (max) 9 29 35 ma i cct (2 oversampling) 10, 11 80 120 ma i cct (4 oversampling) 10, 11 120 170 ma i pll 610 ma sleep mode i dac 0.01 a i cct 85 a notes 1 all measurements are made in 4 oversampling mode unless otherwise speci?ed. 2 temperature range t min to t max : 0 c to 70 c. 3 guaranteed by characterization. 4 for all inputs but pal_ntsc and alsb. 5 for pal_ntsc and alsb inputs. 6 for all outputs but vso /ttx/clamp. 7 for vso /ttx/clamp output. 8 measurement made in 2 oversampling mode. 9 i dac is the total current required to supply all dacs including the v ref circuitry. 10 all six dacs on. 11 i cct or the circuit current, is the continuous current required to drive the digital core without i pll . speci?cations subject to change without notice. (v aa = 5 v, v ref = 1.235 v, r set1,2 = 1200 unless otherwise noted. all speci?ations t min to t max 2 unless otherwise noted.) specifications
? rev. 0 ADV7192?pecifications 3.3 v specifications 1 parameter min typ max unit test conditions static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 1.0 lsb differential nonlinearity 1.0 lsb guaranteed monotonic digital inputs input high voltage, v inh 2v input low voltage, v inl 0.8 v input leakage current 3 1 a input leakage current 4 200 a input current, i in 1 av in = 0.4 v or 2.4 v input capacitance, c in 610 pf digital outputs output high voltage, v oh 2.4 v i source = 400 a output low voltage, v ol 0.4 v i sink = 3.2 ma three-state leakage current 5 10 a three-state leakage current 6 200 a three-state output capacitance 6 10 pf analog outputs output current (max) 4.125 4.33 4.625 ma r l = 300 ? output current (min) 2.16 ma r l = 600 ? , r set1,2 = 2400 ? dac-to-dac matching 0.4 2.5 % output compliance, v oc 1.4 v output impedance, r out 100 k ? output capacitance, c out 6pfi out = 0 ma voltage reference reference range, v ref 7 1.235 v i vrefout = 20 a power requirements v aa 3.15 3.3 3.6 v normal power mode i dac (max) 8 29 ma i cct (2 oversampling) 9, 10 42 54 ma i cct (4 oversampling) 9, 10 68 86 ma i pll 6ma sleep mode i dac 10 0.01 a i cct 85 a notes 1 all measurements are made in 4 oversampling mode unless otherwise speci?ed and are guaranteed by characterization. in 2 oversampling mode, power require- ment for the ADV7192 is typically 3.0 v. 2 temperature range t min to t max : 0 c to 70 c. 3 for all inputs but pal_ntsc and alsb. 4 for pal_ntsc and alsb inputs. 5 for all outputs but vso /ttx/clamp. 6 for vso /ttx/clamp output. 7 measurement made in 2 oversampling mode. 8 i dac is the total current required to supply all dacs including the v ref circuitry. 9 all six dacs on. 10 i cct or the circuit current, is the continuous current required to drive the digital core without i pll . speci?cations subject to change without notice. (v aa = 3.3 v, v ref = 1.235 v, r set1,2 = 1200 unless otherwise noted. all speci?ations t min to t max 2 unless otherwise noted.)
? rev. 0 ADV7192 5 v dynamic?pecifications 1 parameter min typ max unit test conditions hue accuracy 0.5 degrees color saturation accuracy 0.7 % chroma nonlinear gain 0.7 0.9 % referenced to 40 ire chroma nonlinear phase 0.5 degrees chroma/luma intermod 0.1 % chroma/luma gain ineq 1.7 % chroma/luma delay ineq 2.2 ns luminance nonlinearity 0.6 0.7 % chroma am noise 82 db chroma pm noise 72 db differential gain 3 0.1 (0.4) 0.3 (0.5) % differential phase 3 0.4 (0.15) 0.5 (0.3) degrees snr (pedestal) 3 78.5 (78) db rms rms 78 (78) db p-p peak periodic snr (ramp) 3 61.7 (61.7) db rms rms 62 (63) db p-p peak periodic notes 1 all measurements are made in 4 oversampling mode unless otherwise speci?ed and are guaranteed by characterization. 2 temperature range t min to t max : 0 c to 70 c. 3 values in parentheses apply to 2 oversampling mode. speci?cations subject to change without notice. 3.3 v dynamic?pecifications 1 parameter min typ max unit test conditions hue accuracy 0.5 degrees color saturation accuracy 0.8 % luminance nonlinearity 0.6 % chroma am noise 83 db chroma pm noise 71 db chroma nonlinear gain 0.7 % referenced to 40 ire chroma nonlinear phase 0.5 degrees chroma/luma intermod 0.1 % differential gain 3 0.2 (0.5) % differential phase 3 0.5 (0.2) degrees snr (pedestal) 3 78.5 (78) db rms rms 78 (78) db p-p peak periodic snr (ramp) 3 62.3 (62) db rms rms 61 (62.5) db p-p peak periodic notes 1 all measurements are made in 4 oversampling mode unless otherwise speci?ed and are guaranteed by characterization. 2 temperature range t min to t max : 0 c to 70 c. 3 values in parentheses apply to 2 oversampling mode. speci?cations subject to change without notice. (v aa = 5 v 250 mv, v ref = 1.235 v, r set1,2 = 1200 unless otherwise noted. all speci?ations t min to t max 2 unless otherwise noted.) (v aa = 3.3 v 150 mv, v ref = 1.235 v, r set1,2 = 1200 unless otherwise noted. all speci?ations t min to t max 2 unless otherwise noted.)
ADV7192 ? rev. 0 5 v timing characteristics parameter min typ max unit test conditions mpu port 2 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period the first clock is generated setup time (start condition), t 4 0.6 s relevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s analog outputs 2 analog output delay 8 ns dac analog output skew 0.1 ns clock control and pixel port 3 f clock 27 mhz clock high time, t 9 82 ns clock low time, t 10 83 ns data setup time, t 11 6 2.5 ns data hold time, t 12 5 2.0 ns control setup time, t 11 6ns control hold time, t 12 4ns digital output access time, t 13 13 ns digital output hold time, t 14 12 ns pipeline delay, t 15 (2 oversampling) 57 clock cycles pipeline delay, t 15 (4 oversampling) 67 clock cycles teletext port 4 digital output access time, t 16 11 ns data setup time, t 17 3ns data hold time, t 18 6ns reset control reset low time 3 20 ns pll 2 pll output frequency 54 mhz notes 1 temperature range t min to t max : 0 c to 70 c. 2 guaranteed by characterization. 3 pixel port consists of: data: p7Cp0, y0/p8Cy7/p15 pixel inputs control: hsync , vsync , blank clock: clkin 4 teletext port consists of: digital output: ttxrq data: ttx speci?cations subject to change without notice. (v aa = 5 v 250 mv, v ref = 1.235 v, r set1,2 = 1200 v unless otherwise noted. all speci?ations t min to t max 1 unless otherwise noted.)
ADV7192 ? rev. 0 3.3 v timing characteristics parameter min typ max unit test conditions mpu port sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period the first clock is generated setup time (start condition), t 4 0.6 s relevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 2 s analog outputs analog output delay 8 ns dac analog output skew 0.1 ns clock control and pixel port 3 f clock 27 mhz clock high time, t 9 82 ns clock low time, t 10 83 ns data setup time, t 11 64 ns data hold time, t 12 4 2.0 ns control setup time, t 11 2, 5 ns control hold time, t 12 3ns digital output access time, t 13 13 ns digital output hold time, t 14 12 ns pipeline delay, t 15 (2 oversampling) 37 clock cycles teletext port 4 digital output access time, t 16 11 ns data setup time, t 17 3ns data hold time, t 18 6ns reset control reset low time 3 20 ns pll pll output frequency 54 mhz notes 1 temperature range t min to t max : 0 c to 70 c. 2 guaranteed by characterization. 3 pixel port consists of: data: p7Cp0, y0/p8Cy7/p15 pixel inputs control: hsync , vsync , blank clock: clkin 4 teletext port consists of: digital output: ttxrq data: ttx speci?cations subject to change without notice. (v aa = 3.3 v 150 mv, v ref = 1.235 v, r set1,2 = 1200 unless otherwise noted. all speci?ations t min to t max 1 unless otherwise noted.) 2
ADV7192 ? rev. 0 t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sda scl figure 1. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync , vsync , blank cb y cr y cb y hsync , vsync , blank , cso_hso , vso , clamp t 13 t 14 control i/ps control o/ps figure 2. pixel and control data timing diagram t 16 t 17 t 18 txtreq clock txt 4 clock cycles 4 clock cycles 4 clock cycles 3 clock cycles 4 clock cycles figure 3. teletext timing diagram t 9 t 10 t 12 y0 y1 y2 y3 y4 y5 cb0 cb1 cb2 cb3 cb4 cb5 cr0 cr1 cr2 cr3 cr4 cr5 t 11 clock y0 C y9 including sync information cb0 C cb9 cr0 C cr9 progressive scan input figure 4. progressive scan input timing
ADV7192 9 rev. 0 absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital input pin . . gnd C 0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . 150 c body temperature (soldering, 10 secs) . . . . . . . . . . . . . 220 c analog outputs to gnd 2 . . . . . . . . . . . . gnd C 0.5 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an inde?nite duration. package thermal performance the 80-lead package is used for this device. the junction-to- ambient ( ja ) thermal resistance in still air on a four-layer pcb is 24.7 c. to reduce power consumption when using this part the user can run the part on a 3.3 v supply, turn off any unused dacs. the user must at all times stay below the maximum junction temperature of 110 c. the following equation shows how to calculate this junction temperature: j unction temperature = ( v aa ( i dac + i cct )) j a + 70 c t amb i dac = 10 ma + ( sum of the average currents consumed by each powered-on dac ) average current consumed by each powered-on dac = ( v ref k )/ r set v ref = 1.235 v k = 4.2146 ordering guide model temperature range package description package option ADV7192kst 0 c to 70 c 80-lead quad flatpack st-80 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7192 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration nc = no connect p0 p1 p2 p3 p4 p5 p6 p7 nc nc y[0]/p8 y[1]/p9 y[2]/p10 y[3]/p11 y[4]/p12 y[5]/p13 y[6]/p14 y[7]/p15 y[8] y[9] v ref comp 1 dac a dac b v aa agnd dac c dac d agnd v aa dac e dac f comp 2 r set2 dgnd reset pal_ntsc r set1 alsb screset/rtc/tr dgnd hsync vsync blank ttxreq dgnd v dd agnd v aa scl sda clkin clkout v dd cb[4] cb[5] cb[6] cb[7] cb[8] cb[9] 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin 1 identifier top view (not to scale) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 dgnd v dd cb[3] dgnd vso / ttx/clamp cso_hso cb[2] cb[1] cb[0] cr[9] cr[8] cr[7] cr[6] cr[5] v dd cr[4] cr[3] cr[2] cr[1] cr[0] ADV7192 lqfp
ADV7192 10 rev. 0 pin function descriptions pin input/ no. mnemonic output function 1, 2 nc no connect. 3C10 p0Cp7 i 8-bit 4:2:2 multiplexed ycrcb pixel port. the lsb of the input data is set up on pin p0 (pin number 3). 11C18 y0/p8Cy7/p15 i 16-bit 4:2:2 multiplexed ycrcb pixel port (bits 8C15). 1 10-bit progressive scan input for ydata (bits 0C7). 19, 20 y8Cy9 1 10-bit progressive scan input is ydata (bits 8 and 9). 21, 34, 68, 79 v dd p digital power supply (3.3 v to 5 v). 22, 33, 43, 69, dgnd g digital ground. 80 23 hsync i/o hsync (modes 1, 2, and 3) control signal. this pin may be con?gured to be an output (master mode) or an input (slave mode) and accept sync signals. 24 vsync i/o vsync control signal. this pin may be con?gured as an output (master mode) or as an input (slave mode) and accept vsync as a control signal. 25 blank i/o video blanking control signal. this signal is optional. for further information see vertical blanking and data insertion blanking input section. 26C31, 75C78 cb4Ccb9, cb0Ccb3 i 1 10-bit progressive scan input port for cb data. 32 ttxreq o teletext data request output signal, used to control teletext data transfer. 35, 49, 52 agnd g analog ground. 36 clkin i ttl clock input. requires a s table 27 mhz reference clock for sta ndard operation. alterna tively, a 24.5454 mhz (ntsc) or 29.5 mhz (pal) can be used for square pixel operation. 37 clkout o clock output pin. 38, 48, 53 v aa p analog power supply (3.3 v to 5 v). 39 scl i mpu port serial interface clock input. 40 sda i/o mpu port serial data input/output. 41 screset/ i multifunctional input: real time control (rtc) input, timing reset input, subcarrier rtc/tr reset input. 42 alsb i ttl address input. this signal sets up the lsb of the mpu address. 44 r set2 i a 1200 ? resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals from the dac d, e, f. 45 comp 2 o compensation pin for dacs d, e, and f. connect a 0.1 f capacitor from comp2 to v aa . 46 dac f o s-video c/p r/v/red analog output. this dac is capable of providing 4.33 ma output. 47 dac e o s-video y/pb/u/blue analog output. this dac is capable of providing 4.33 ma output. 50 dac d o composite/y (progressive scan)/y/green analog output. this dac is capable of providing 4.33 ma output. 51 dac c o s-video c/pr/v/red analog output. this dac is capable of providing 4.33 ma output. 54 dac b o s-video y/pb/u/blue analog output. this dac is capable of providing 4.33 ma out put. 55 dac a o composite/y(progressive scan)/y/green analog output. this dac is capable of providing 4.33 ma out put. 56 comp 1 o compensation pin for dacs a, b, and c. connect a 0.1 f capacitor from comp1 to v aa . 57 v ref i/o voltage reference input for dacs or voltage reference output (1.235 v). an external v ref cannot be used in 4 oversampling mode. 58 r set1 i a 1200 ? resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals from the dac a, b, c. 59 pal_ntsc i input signal to select pal or ntsc mode of operation, pin set to logic 1 selects pal. 60 reset i the input resets the on-chip timing generator and sets the ADV7192 into default mode. see appendix 8 for default register settings. 61 cso_hso o dual function cso or hso output sync signal at ttl level. 62 vso /ttx/clamp i/o multif unctional pin. vso output sync signal at ttl level. teletext data input pin. clamp ttl output signals can be used to drive external circuitry to enable clamping of all video signals. 63C67, 70C74 cr0Ccr4, cr5Ccr9 i 1 10-bit progressive scan input port for cr data.
ADV7192 11 rev. 0 detailed description of features clocking: single 27 mhz clock required to run the device 4 oversampling with internal 54 mhz pll square pixel operation advanced power management programmable video control features: digital noise reduction black burst signal generation pedestal level hue, brightness, contrast, and saturation clamping output signal vbi (vertical blanking interval) subcarrier frequency and phase luma delay chroma delay gamma correction luma and chroma filters luma ssaf (super subalias filter) average brightness detection field counter interlaced/noninterlaced operation complete on-chip video timing generator programmable multimode master/slave operation macrovision rev 7.1 cgms (copy generation management system) wss (wide screen signaling) closed captioning support teletext insertion port (pal-wst) 2-wire serial mpu interface (i 2 c-compatible and fast i 2 c) i 2 c registers synchronized to vsync general description the ADV7192 is an integrated digital video encoder that converts digital ccir-601/656 4:2:2 8-bit or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. additionally, it is pos sible i n t e r p o l a t o r modulator and hue control brightness control and add sync and interpolator saturation control and add burst and interpolator programmable luma filter and sharpness filter programmable chroma filter sin/cos dds block real-time control circuit screset/rtc/tr i n t e r p o l a t o r m u l t i p l e x e r yuv-to-rgb matrix and yuv level control block y0 C y9 cb0 C cb9 cr0 C cr9 10-bit dac 10-bit dac 10-bit dac dac control block 10-bit dac 10-bit dac 10-bit dac dac control block dac a dac b dac c v ref r set2 comp2 dac d dac f dac e r set1 comp1 dnr and gamma correction 10 10 10 v u y ycrcb- to- yuv matrix 10 10 10 v u y pll demux 10 10 10 teletext insertion block video timing generator cgms/wss and closed captioning control i 2 c mpu port alsb sda scl pal_ntsc vso /clamp cso_hso hsync vsync blank reset ttx ttxrq p0 p15 clkin clkout ADV7192 figure 5. detailed functional block diagram to input video data in 3 10-bit ycrcb progressive scan format to facilitate interfacing devices such as progressive scan systems. six dacs are available on the ADV7192, each of which is ca pable of providing 4.33 ma of current. in addition to the composite output signal there is the facility to output s-video (y/c video), rgb video and yuv video. all yuv formats (smptre/ebu n10, mii or betacam) are supported. the on-board ssaf (super subalias filter) with extended lumi- nance frequency response and sharp stopband attenuation enables studio quality video playback on modern tvs, giving optimal horizontal line resolution. an additional sharpness control feature allows high-frequency enhancement on the luminance signal. subtract signal in threshold range from original signal filter output >threshold? filter output< threshold input filter block main signal path noise signal path y data input dnr out add signal above threshold range to original signal dnr control block size control border area block offset gain coring gain data coring gain border dnr sharpness mode filter output threshold input filter block main signal path noise signal path y data input dnr out dnr control block size control border area block offset gain coring gain data coring gain border dnr mode figure 6. block diagram for dnr mode and dnr sharpness mode
ADV7192 12 rev. 0 digital noise reduction allows improved picture quality in remov- ing low amplitude, high frequency noise. figure 6 shows the dnr functionality in the two modes available. programmable gamma correction is also available. the figure below shows the response of different gamma values to a ramp signal. 250 200 150 100 50 0 300 signal outputs signal input 0.5 gamma correction block output to a ramp input for various gamma values gamma-corrected amplitude 0 50 100 150 200 250 location 0.3 1.5 1.8 figure 7. signal input (ramp) and selectable gamma output curves the device is driven by a 27 mhz clock. data can be output at 27 mhz or 54 mhz (on-board pll) when 4 oversampling is enabled. also, the output filter requirements in 4 oversam pling and 2 oversampling differ, as can be seen in figure 8. C 30db 0db 6.75mhz 13.5mhz 27.0mhz 40.5mhz 54.0mhz 2 filter requirements 4 filter requirements figure 8. output filter requirements in 4 oversam pling mode encoder core 2 i n t e r p o l a t i o n 6 d a c o u t p u t s 54mhz output rate ADV7192 pll 54mhz mpeg2 pixel bus 27mhz figure 9. pll and 4 oversampling block diagram the ADV7192 also supports both pal and ntsc square pixel operation. in this case the encoder requires a 24.5454 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode op era- tion. all internal timing is generated on-chip. an advanced power management circuit enables optimal control of power consumption in normal operating modes or sleep modes. the output video frames are synchronized with the incoming data timing reference codes. optionally, the encoder accepts (and can generate) hsync , vsync, and field timing sig nals. these timing signals can be adjusted to change pulsewidth and position while the part is in master mode. hso / cso and vso ttl outputs are also available and are timed to the analog output video. a separate teletext port enables the user to directly input teletext data during the vertical blanking interval. the ADV7192 also incorporates wss and cgms-a data con trol generation. the ADV7192 modes are set up over a 2-wire serial bidirec tional port (i 2 c-compatible) with two slave addresses, and the device is register-compatible with the adv7172. the ADV7192 is packaged in an 80-lead lqfp package. data path description for pal b, d, g, h, i, m, n, and ntscm, n modes, ycrcb 4:2:2 data is input via the ccir-656/601-compatible pixel port at a 27 mhz data rate. the pixel data is demultiplexed to form three data paths. y typically has a range of 16 to 235, cr and cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both y, cb, and cr. the ADV7192 supports pal (b, d, g, h, i, n, m) and ntscm, n (with and without pedestal) and pal60 standards. digital noise reduction can be applied to the y signal. pro- grammable gamma correction can also be applied to the y signal if required. the y data can be manipulated for contrast control and a setup level can be added for brightness control. the cr, cb data can be scaled to achieve color saturation control. all settings become effective at the start of the next ?eld when double buffering is enabled. the appropriate sync, blank, and burst levels are added to the ycrcb data. macrovision antitaping, closed-captioning and teletext levels are also added to y and the resultant data is inter- polated to 54 mhz (4 oversampling mode). the interpolated data is ?ltered and scaled by three digital fir ?lters. the u and v signals are modulated by the appropriate subcarrier sine/cosine waveforms and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. the resulting u and v signals are added together to make up the chrominance signal. the luma (y) signal can be delayed by up to six clock cycles (at 27 mhz) and the chroma signal can be delayed by up to eight clock cycles (at 27 mhz). the luma and chroma signals are added together to make up the composite video signal. all timing signals are controlled. the ycrcb data is also used to generate rgb data with appropri- ate sync and blank levels. the yuv levels are scaled to output the suitable smpte/ebu n10, mii, or betacam levels. each dac can be individually powered off if not required. a complete description of dac output con?gurations is given in the mode register 2 section. video output levels are illustrated in appendix 9.
ADV7192 13 rev. 0 table i. luminance internal filter speci?ations (4 oversampling) passband 3 db bandwidth 2 stopband stopband filter type filter selection ripple 1 (db) (mhz) cutoff 3 (mhz) attentuation 4 (db) mr04 mr03 mr02 low-pass (ntsc) 0 0 0 0.16 4.24 6.05 C75.2 low-pass (pal) 0 0 1 0.1 4.81 6.41 C64.6 notch (ntsc) 0 1 0 0.09 2.3/4.9/6.6 8.03 C87.3 notch (pal) 0 1 1 0.1 3.1/5.6/6.4 8.02 C79.7 extended (ssaf) 1 0 0 0.04 6.45 8.03 C86.6 cif 1 0 1 0.127 3.02 5.04 C62.6 qcif 1 1 0 monotonic 1.5 3.74 C88.2 notes 1 passband ripple is de?ned as the fluctuations from the 0 db response in the passband, measured in (db). the passband is de?ned to have 0Cfc frequency limits for a low-pass ?lter, 0Cf1 and f2Cin?nity for a notch ?lter, where fc, f1, f2 are the C3 db points. 2 3 db bandwidth refers to the C3 db cutoff frequency. 3 stopband cutoff refers to the frequency at the attenuation point referred to under note 4. 4 stopband attenuation refers to the attenuation point (db) at the frequency referred to under note 3. table ii. chrominance internal filter speci?ations (4 oversampling) passband 3 db bandwidth 2 stopband stopband filter type filter selection ripple 1 (db) (mhz) cutoff 3 (mhz) attentuation 4 (db) mr07 mr06 mr05 1.3 mhz low-pass 0 0 0 0.09 1.395 2.46 C83.9 0.65 mhz low-pass 0 0 1 monotonic 0.65 2.41 C71.1 1.0 mhz low-pass 0 1 0 monotonic 1.0 1.89 C64.43 2.0 mhz low-pass 0 1 1 0.048 2.2 3.1 C65.9 3.0 mhz low-pass 1 0 0 monotonic 3.2 5.3 C84.5 cif 1 0 1 monotonic 0.65 2.41 C71.1 qcif 1 1 0 monotonic 0.5 1.75 C33.1 notes 1 passband ripple is de?ned as the fluctuations from the 0 db response in the passband, measured in (db). the passband is de?ned to have 0Cfc frequency limits for a low-pass ?lter, 0Cf1 and f2Cin?nity for a notch ?lter, where fc, f1, f2 are the C3 db points. 2 3 db bandwidth refers to the C3 db cutoff frequency. 3 stopband cutoff refers to the frequency at the attenuation point referred to under note 4. 4 stopband attenuation refers to the attenuation point (db) at the frequency referred to under note 3. when used to interface progressive scan systems, the ADV7192 allows input to ycrcb signals in progressive scan format (3 10-bit) before these signals are routed to the interpolation ?lters and the dacs. internal filter response the y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost/attenuation, a cif response, and a qcif response. the uv/filter supports several different frequency responses including ?ve low-pass responses, a cif response, and a qcif response, as can be seen in the following ?gures. all filter plots show the 4 oversampling responses. in extended mode there is the option of 12 responses in the range from C4 db to +4 db. the desired response can be chosen by the user by programming the correct value via the i 2 c. the varia tion of frequency responses can be seen in the tables i and ii. for more detailed filter plots refer to analog devices application note an-562.
ADV7192 14 rev. 0 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 frequency C mhz magnitude C db figure 10. ntsc low-pass luma filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 frequency C mhz magnitude C db figure 11. pal low-pass luma filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 12. ntsc notch luma filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 13. pal notch luma filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 14. extended mode (ssaf) luma filter 4 0 0 C 8 C 6 C 2 2 1 2 67 3 5 C 12 C 4 magnitude C db frequency C mhz C 10 4 figure 15. extended ssaf luma filter and program mable gain/attenuation showing + 4 db/ 12 db range
ADV7192 15 rev. 0 1 0 C 4 C 3 C 1 0 1 2 67 3 5 C 5 C 2 magnitude C db frequency C mhz 4 figure 16. extended ssaf and programmable attenua tion, showing range 0 db/ 4db 5 0 0 1 3 4 1 2 67 3 5 C 1 2 magnitude C db frequency C mhz 4 figure 17. extended ssaf and programmable gain, showing range 0 db/+4 db 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 18. luma cif filter 0 C 20 0 C 50 C 60 C 30 C 10 24 1012 68 C 70 C 40 magnitude C db frequency C mhz figure 19. luma qcif filter 0 C 20 0 C 50 C 60 C 30 C 10 24 1012 68 C 70 C 40 magnitude C db frequency C mhz figure 20. chroma 0.65 mhz low-pass filter 0 C 20 0 C 50 C 60 C 30 C 10 24 1012 68 C 70 C 40 magnitude C db frequency C mhz figure 21. chroma 1.0 mhz low-pass filter
ADV7192 16 rev. 0 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 22. chroma 1.3 mhz low-pass filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 23. chroma 2 mhz low-pass filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 24. chroma 3 mhz low-pass filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 25. chroma cif filter 0 C 20 0 C 50 C 60 C 30 C 10 2 4 10 12 68 C 70 C 40 magnitude C db frequency C mhz figure 26. chroma qcif filter
ADV7192 17 rev. 0 features: functional description black burst output it is possible to output a black burst signal from two dacs. this signal output is very useful for professional video equipment since it enables two video sources to be locked together. (mode register 9.) black burst output cvbs cvbs digital data generator ADV7192 digital data generator ADV7192 figure 27. possible application for the black burst output signal brightness detect this feature is used to monitor the average brightness of the incoming y video signal on a ?eld by ?eld basis. the informa tion is read from the i 2 c and based on this information the color saturation, contrast and brightness controls can be ad justed (for example to c ompens ate for very dark pictures). (brightness detect register.) chroma/luma delay the luminance data can be delayed by maximum of six clock cycles. additionally the chroma can be delayed by a maximum of eight clock cycles (one clock cycle at 27 mhz). (timing reg- ister 0 and mode register 9.) chroma delay luma delay figure 28. chroma delay figure 29. luma delay clamp output the ADV7192 has a programmable clamp ttl output signal. this clamp signal is programmable to the front and back porch. the clamp signal can be varied by one to three clock cycles in a positive and negative direction from the default position. (mode register 5, mode register 7.) cvbs output pin clamp output pin mr57 = 1 mr57 = 0 clamp o/p signals figure 30. clamp output timing cso , hso and vso outputs the ADV7192 supports three output timing signals, cso (composite sync signal), hso (horizontal sync signal) and vso (vertical sync signal). these output ttl signals are a ligned with the analog video outputs. see figure 31 for an example of these waveforms. (mode register 7.) output video 5251234567891011 C 19 example:- ntsc cso hso vso figure 31. cso , hso , vso timing diagram color bar generation the ADV7192 can be con?gured to generate 100/7.5/75/7.5 color bars for ntsc or 100/0/75/0 color bars for pal. (mode register 4.) color burst signal control the burst information can be switched on and off the composite and chroma video output. (mode register 4.) color controls the ADV7192 allows the user to control the brightness, contrast, hue and saturation of the color. the control registers may be double-buffered, meaning that any modi?cation to the registers will be done outside the active video region and, therefore, changes made will not be visible during active video. contrast control contrast adjustment is achieved by scaling the y input data by a factor programmed by the user. this factor allows the data to be scaled between 0% and 150%. (contrast control register.) brightness control the brightness is controlled by adding a programmable setup level onto the scaled y data. this brightness level may be added onto the y data. for ntsc with pedestal, the setup can vary from 0 ire to 22.5 ire. for ntsc without pedestal and pal, the setup can vary from C7.5 ire to +15 ire. (brightness control register.) color saturation color adjustment is achieved by scaling the cr and cb input data by a factor programmed by the user. this factor allows the data to be scaled between 0% and 200%. (u scale register and v scale register.) hue adjust control the hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodi?ed, i.e., only the phase between the video and the colorburst is modi?ed and hence the hue is shifted. the ADV7192 provides a range of 22 in increments of 0.17578125 . (hue adjust register.) chrominance control the color information can be switched on and off the com- posite, chroma and color component video outputs. (mode register 4.)
ADV7192 18 rev. 0 undershoot limiter a limiter is placed after the digital ?lters. this prevents any synchronization problems for tvs. the level of undershoot is programmable between C1.5 ire, C6 ire, C11 ire when oper- ating in 4 oversampling mode. in 2 oversampling mode the limits are C7.5 ire and 0 ire. (mode register 9 and timing register 0.) digital noise reduction dnr is applied to the y data only. a ?lter block selects the high frequency, low amplitude components of the incoming signal (dnr input select). the absolute value of the ?lter output is compared to a programmable threshold value (dnr thresh- old control). there are two dnr modes available: dnr mode and dnr sharpness mode. in dnr mode, if the absolute value of the ?lter output is smaller than the threshold, it is assumed to be noise. a programmable amount (coring gain control) of this noise signal will be sub- tracted from the original signal. in dnr sharpness mode, if the absolute value of the ?lter output is less than the programmed threshold, it is assumed to be noise, as before. otherwise, if the level exceeds the threshold, now being identi?ed as a valid signal, a fraction of the signal (coring gain control) will be added to the original signal in order to boost high frequency components and to sharpen the video image. in mpeg systems it is common to process the video information in blocks of 8 8 pixels for mpeg2 systems, or 16 16 pixels for mpeg1 systems ('block size control'). dnr can be applied to the resulting block transition areas that are known to contain noise. generally the block transition area contains two pixels. it is possible to de?ne this area to contain four pixels (border area control). it is also possible to compensate for variable block positioning or differences in ycrcb pixel timing with the use of the block offset control. (mode register 8, dnr registers 0C2.) double buffering double buffering can be enabled or disabled on the following registers: closed captioning registers, brightness control reg- ister, v-scale, u-scale contrast control register, hue adjust register, macrovision registers, and the gamma curve select bit. these registers are updated once per ?eld on the falling edge of the vsync signal. double buffering improves the overall performance of the ADV7192, since modi?cations to register settings will not be made during active video, but take effect on the start of the active video. (mode register 8.) gamma correction control gamma correction may be performed on the luma data. the user has the choice to use either of two different gamma curves, a or b. at any one time one of these curves is operational if gamma correction is enabled. gamma correction allows the mapping of the luma data to a user-de?ned function. (mode register 8, gamma correction registers 0C13.) ntsc pedestal control in ntsc mode it is possible to have the pedestal signal gener- ated on the output video signal. (mode register 2.) power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset pin. this initializes the pixel port such that the data on the pixel inputs pins is ignored. see appendix 8 for the register settings after reset is applied. progressive scan input it is possible to input data to the ADV7192 in progressive scan format. for this purpose the input pins y0/p8Cy7/p15, y8Cy9, cr0Ccr9 and cb0Ccb9 accept 10-bit y data, 10-bit cb data and 10-bit cr data. the data is clocked into the part at 27 mhz. the data is then ?ltered and sinc corrected in an 2 interpo- lation ?lter and then output to three video dacs at 54 mhz (to interface to a progressive scan monitor). frequency C mhz 0 030 5 amplitude C db 10 15 20 25 C 10 C 20 C 30 C 50 C 60 C 40 C 70 figure 32. plot of the interpolation filter for the y data frequency C mhz 0 030 5 amplitude C db 10 15 20 25 C 10 C 20 C 30 C 50 C 60 C 40 C 70 figure 33. plot of the interpolation filter for the crcb data it is assumed that there is no color space conversion or any other such operation to be performed on the incoming data. thus if these dac outputs are to drive a tv, all relevant timing and synchronization data should be co ntained in the incoming digital y data. the block diagram below shows a possible con?guration for progressive scan mode using the ADV7192.
ADV7192 19 rev. 0 27mhz 54mhz 6 d a c o u t p u t s encoder ADV7192 mpeg2 pll encoder core pixel bus i n t e r p o l a t i o n 2 progressive scan decoder 30-bit interface figure 34. block diagram using the ADV7192 in progres- sive scan mode the progressive scan decoder deinterlaces the data from the mpeg2 decoder. this now means that there are 525 video lines per ?eld in ntsc mode and 625 video lines per ?eld in pal mode. the duration of the video line is now 32 s. it is important to note that the data from the mpeg2 decoder is in 4:2:2 format. the data output from the progressive scan decoder is in 4:4:4 format. thus it is assumed that some form of interpolation on the color component data is performed in the progressive scan decoder ic. (mode register 8.) real-time control, subcarrier reset, and timing reset together with the screset/rtc/tr pin and mode regis ter 4 (genlock control), the ADV7192 can be used in (a) timing reset mode, (b) subcarrier phase reset mode or (c) rtc mode. (a) a timing reset is achieved in holding this pin high. in this state the horizontal and vertical counters will remain reset. on releasing this pin (set to low), the internal counters will commence counting again. the minimum time the pin has to be held high is 37 ns (1 clock cycle at 27 mhz), other wise the reset signal might not be recognized. (b) the subcarrier phase will reset to that of field 0 at the start of the following ?eld when a low to high transition occurs on this input pin. (c) in rtc mode, the ADV7192 can be used to lock to an ex- ternal video source. the real-time control mode allows the ADV7192 to auto- matically alter the subcarrier fr equency to compensate for line length variations. when the part is connected to a device that outputs a digital datastream in the rtc format (such as a adv7185 video decoder, see figure 38), the part will automatically change to the compensated subcarrier freq uency on a line-by-line basis. this digital datastream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is two clock cycles long. 00hex should be written i nto all four subcarrier frequency registers when using this mode. (mode register 4.) sch phase mode the sch phase is con?gured in default mode to reset every four (ntsc) or eight (pal) ?elds to avoid an accumulation of sch phase error over time. in an ideal system, zero sch phase error would be maintained forever, but in reality, this is impos- sible to achieve due to clock frequency variations. this effect is reduced by the use of a 32-bit dds, which generates this sch. resetting the sch phase every four or eight ?elds avoids the accumulation of sch phase error, and results in very minor sch phase jumps at the start of the four or eight ?eld sequence. resetting the sch phase should not be done if the video source does not have stable timing or the ADV7192 is con?gured in rtc mode. under these conditions (unstable video) the subcarrier phase reset should be enabled but no reset applied. in this con?guration the sch phase will never be reset; this means that the output video will now track the unstable input video. the sub- carrier phase reset when applied will reset the sch phase to field 0 at the start of the next ?eld (e.g., subcarrier phase reset ap plied in field 5 (pal) on the start of the next ?eld sch phase will be reset to field 0). (mode register 4.) sleep mode if, after reset , the screset/rtc/tr and ntsc_pal pins are both set high, the ADV7192 will power up in sleep mode to facilitate low power consumption before all registers have been initialized. if power-up in sleep mode is disabled, sleep mode control passes to the sleep mode control in mode register 2 (i.e., con- trol via i 2 c). (mode register 2 and mode register 6.) square pixel mode the ADV7192 can be used to operate in square pixel mode. for ntsc operation an input clock of 24.5454 mhz is requ ired. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accordingly for square pixel mode operation. square pixel mode is not available in 4 oversampling mode. (mode register 2.) vertical blanking data insertion and blank input it is possible to allow encoding of incoming ycbcr data on those lines of vbi that do not have line sync or pre-/post-equal- ization pulses . this mode of operation is called partial blanking . it allows the insertion of any vbi data (opened vbi) into the encoded output waveform, this data is present in digitized incoming ycbcr data stream (e.g., wss data, cgms, vps etc.). alternatively the entire vbi may be blanked (no vbi data inserted) on these lines. vbi is available in all timing modes. the complete vbi is comprised of the following lines: 525/60 systems, lines 525 to 21 for ?eld one and lines 262 to line 284 for ?eld two. 625/50 systems, lines 624 to line 22 and lines 311 to 335. the opened vbi consists of: 525/60 systems, lines 10 to 21 for ?eld one and second half of line 273 to line 284 for ?eld two. 625/50 systems, lines 7 to 22 and lines 319 to 335. (mode register 3.) it is possible to allow control over the blank signal using timing register 0. when the blank input is enabled (tr03 = 0 and input pin tied low), the blank input can be used to input externally generated blank signals in slave mode 1, 2, or 3. when the blank input is disabled (tr03 = 1 and input pin tied low or tied high) the blank input is not used and the ADV7192 automatically blanks all normally blank lines as per ccir-624. (timing register 0.)
ADV7192 20 rev. 0 yuv levels this functionality allows the ADV7192 to output smpte levels or betacam levels on the y output when con?gured in pal or ntsc mode. sync video betacam 286 mv 714 mv smpte 300 mv 700 mv mii 300 mv 700 mv as the data path is branched at the output of the ?lters, the luma signal relating to the cvbs or s-video y/c output is unaltered. only the y output of the ycrcb outputs is scaled. this control allows color component levels to have a peak-peak amplitude of 700 mv, 1000 mv or the default values of 934 mv in ntsc and 700 mv in pal. (mode register 5.) 16-bit interface it is possible to input data in 16-bit format. in this case, the interface only operates if the data is accompanied by separate hsync / vsync / blank signals. sixteen-bit mode is not available in slave mode 0 since eav/sav timing codes are used. (mode register 8.) 4 oversampling and internal pll it is possible to operate all six dacs at 27 mhz (2 oversam- pling) or 54 mhz (4 oversampling). the ADV7192 is supplied with a 27 mhz clock synced with the incoming data. two options are available: to run the d evice throughout at 27 mhz or to enable the pll. in the latter case, even if the incoming data runs at 27 mhz, 4 oversampling and the internal pll will output the data at 54 mhz. note in 4 oversampling mode the requirements for the optional output ?lters are different from those in 2 oversampling. (mode register 1, mode register 6.) see appendix 6. encoder core 2 i n t e r p o l a t i o n 6 d a c o u t p u t s 54mhz output encode ADV7192 pll 54mhz mpeg2 pixel bus 27mhz figure 35. pll and 4 oversampling block diagram C 30db 0db 6.75mhz 13.5mhz 27.0mhz 40.5mhz 54.0mhz 2 filter requirements 4 filter requirements figure 36. o utput filter requirements in 2 and 4 over- sampling mode video timing description the ADV7192 is intended to interface to off-the-shelf mpeg1 and mpeg2 decoders. as a consequence, the ADV7192 accepts 4:2:2 ycrcb pixel data via a ccir-656 pixel port and has several video timing modes of operation that allow it to be con?gured as either system master video timing generator or a slave to the system video timing g enerator. the ADV7192 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. the ADV7192 calculates the width and placement of analog sync pulses, blanking levels, and color bu rst envelopes. color bursts are disabled on appropriate lines and serration and equal- ization pulses are inserted where required. in addition the ADV7192 supports a pal or ntsc square pixel operation. the part requires an input pixel clock of 24.5454 mhz for ntsc square pixel operation and an input pixel clock of 29.5 mhz for pal square pixel operation. the internal horizontal line counters place the various video waveform sections in the cor- rect location for the new clock frequencies. the ADV7192 has four distinct master and four distinct slave timing con?gurations. timing control is established with the bidirectional hsync , blank and vsync pins. tim- ing register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. (mode regis- ter 2, timing register 0, 1.) reset sequence when reset becomes active the ADV7192 reverts to the default output con?guration (see appendix 8 for register settings). the ADV7192 internal timing is under the control of the logic level on the ntsc_pal pin. when reset is released y, cr, cb values corresponding to a black screen are input to the ADV7192. output timing signals are still suppressed at this stage. dacs a, b, c are switched off and dacs d, e, f are switched on. when the user requires valid data, pixel data valid control is enabled (mr26 = 1) to allow the valid pixel data to pass through the encoder. digital output timing signals become active and the encoder timing is now under the control of the timing regis- ters. if at this stage, the user wishes to select a different video standard to that on the ntsc_pal pin, standard i 2 c control should be enabled (mr25 = 1) and the video standard required is selected by programming mode register 0 (output video stan- dard selection). figure 37 illustrates the reset sequence timing.
ADV7192 21 rev. 0 xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx off 0 digital timing signals suppressed timing active 1 valid video valid video valid video black value black value with sync reset dac d, dac e dac f dac a, dac b, dac c mr26 pixel_data_valid digital timing figure 37. reset sequence timing diagram composite video e.g., vcr or cable m u x hsync vsync clock green/composite/y blue/luma/u ADV7192 p7 C p0 screset/rtc/tr mpeg decoder video decoder adv7185 lcc1 p19 C p12 red/chroma/v green/composite/y blue/luma/u red/chroma/v h/l transition count start low 128 rtc time slot: 01 14 67 68 not used in ADV7192 19 valid sample invalid sample f sc pll increment 1 8/line locked clock 5 bits reserved sequence bit 2 reset bit 3 reserved 4 bits reserved 21 0 13 14 bits reserved 0 notes: 1 f sc pll increment is 22 bits long, value loaded into ADV7192 fsc dds register is f sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the ADV7192. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset ADV7192 s dds gll figure 38. rtc timing and connections
ADV7192 22 rev. 0 mode 0 (ccir?56): slave option (timing register 0 tr0 = x x x x x 0 0 0) the ADV7192 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately before and aft er each line during active picture and retrace. mode 0 is illustrated in figure 39. the hsync , vsync and blank (if not used) pins should be tied high during this mode. blank output is available. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 llnes/60hz) pal system (625 lines/50hz) y figure 39. timing mode 0, slave mode mode 0 (ccir?56): master option (timing register 0 tr0 = x x x x x 0 0 1) the ADV7192 generates h, v, and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir656 standard. the h bit is output on the hsync pin, the v bit is output on the blank pin and the f bit is output on the vsync pin. mode 0 is illustrated in figure 40 (ntsc) and figure 41 (pal). the h, v, and f transitions relative to the video waveform are illustrated in figure 42. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display vertical blank odd field even field h v f display figure 40. timing mode 0, ntsc master mode
ADV7192 23 rev. 0 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 313 display display vertical blank h v f odd field even field figure 41. timing mode 0, pal master mode analog video h f v figure 42. timing mode 0 data transitions, master mode
ADV7192 24 rev. 0 mode 1: slave option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 0) in this mode the ADV7192 accepts horizontal sync and odd/ even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled the ADV7192 automatically blanks all normally blank lines as per ccir-624. mode 1 is illustrated in figure 43 (ntsc) and figure 44 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank field figure 43. timing mode 1, ntsc 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 320 display vertical blank odd field even field hsync blank field display figure 44. timing mode 1, pal
ADV7192 25 rev. 0 mode 1: master option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 1) in this mode the ADV7192 can generate horizontal sync and odd/e ven field signals. a transition of the field input when hsync is low indicates a new frame i.e., vertical retrace. the blank signal is optional. when the blank input is disabled the ADV7192 automatically blanks all normally blank lines as per ccir-624. pixel data is latched on the rising clock edge following the timing signal transitions. mode 1 is illustrated in figure 43 (ntsc) and figure 44 (pal). figure 45 illustrates the hsync , blank and field for an odd or even ?eld transition relative to the pixel data. field pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y hsync blank pal = 132 clock/2 ntsc = 122 clock/2 figure 45. timing mode 1 odd/even field transitions master/slave mode 2: slave option hsync , vsync, blank (timing register 0 tr0 = x x x x x 1 0 0) in this mode the ADV7192 accepts horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled the ADV7192 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 46 (ntsc) and figure 47 (pal). 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank vsync figure 46. timing mode 2, ntsc
ADV7192 26 rev. 0 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 320 display vertical blank odd field even field hsync blank display vsync figure 47. timing mode 2, pal mode 2: master option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 1) in this mode the ADV7192 can generate horizontal and vertical sync signals. a coin cident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled the ADV7192 automatically blanks all normally blank lines as per cc ir-624. mode 2 is illustrated in figure 46 (ntsc) and figure 47 (pal). figure 48 illustrates the hsync , blank and vsync for an even-to-odd ?eld transition relative to the pixel data. figure 49 illustrates the hsync , blank and vsync for an odd-to-even ?eld transition relative to the pixel data. pal = 12 clock/2 ntsc = 16 clock/2 hsync vsync blank pixel data pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y figure 48. timing mode 2, even-to-odd field transition master/slave pal = 864 clock/2 ntsc = 858 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 hsync vsync blank pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y cb figure 49. timing mode 2, odd-to-even field transition master/slave
ADV7192 C27C rev. 0 mode 3: master/slave option hsync , blank , field (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode the ADV7192 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync is high indicates a new frame i.e., vertical retrace. the blank signal is optional. when the blank input is disabled the ADV7192 automatically blanks all normally blank lines as per ccir-624. mode 3 is illustrated in figure 50 (ntsc) and figure 51 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank field figure 50. timing mode 3, ntsc 622 623 624 625 1 2 3 4 5 67 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 320 display vertical blank odd field even field hsync blank field display figure 51. timing mode 3, pal
ADV7192 C28C rev. 0 mpu port description the ADV7192 support a two-wire serial (i 2 c-compatible) microprocessor bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (scl), carry infor mation between any device connected to the bus. each slave device is recognized by a unique address. the ADV7192 has four pos sible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in fi gure 52 and figure 54. the lsb sets either a read or write operation. logic level 1 corresponds to a read operation while logic level 0 corresponds to a write operation. a1 is set by setting the alsb pin of the ADV7192 to logic level 0 or logic level 1. when alsb is set to 0, there is greater input bandwidth on the i 2 c lines, w hich allows high speed data transfers on this bus. when alsb is set to 1, there is reduced input bandwidth on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal controller. this mode is recommended for noisy systems. 1 x 10101a1 address control setup by alsb read/write control 0 write 1 read figure 52. slave address to control the various devices on the bus the following protocol must be followed. first, the master initiates a data transfer by establishing a start condition, de?ed by a high-to-low transition on sda while scl remains high. this indicates that an address/ data stream will follow. all peripherals respond to the start con- dition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowl- edge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and scl lines waiting for the start condi tion and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the ?st byte means that the master will write information to the peripheral. a logic 1 on the lsb of the ?st byte means that the master will read information from the peripheral. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a (s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m ) data p write sequence read sequence a (s) = no acknowledge by slave a (m) = no acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit figure 54. write and read sequences the ADV7192 acts as a standard slave device on the bus. the data on the sda pin is eight bits long supporting the 7-bit addresses plus the r/ w bit. it interprets the ?st byte as the device address and the second byte as the starting subaddress. the subaddresses autoincrement allowing data to be written to or read from the starting subaddress. a data transfer is always termi nated by a stop condition. the user can also access any unique su baddress register on a one-by-one basis without having to update all the registers. there is one exception. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the autoincrement function should be then used to increment and access subcarrier frequency registers 1, 2, and 3. the subcarrier frequency r egisters should not be accessed independently. stop and start conditions can be detected at any stage du ring the data transfer. if these conditions are asserted out of sequence with normal read and write operations, then, these cause an immediate jump to the idle condition. during a given scl high period the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7192 will not issue an acknowledge and will return to the idle condition. if, in autoincrement mode, the user exceeds the highest subaddress, then the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be ou tput until the master dev ice issues a no-acknowledge. this indicates the end of a read. a no-acknowledge condition is where the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7192 and the part will return to the idle condition. 89 1 7 89 17 89 p s start addr r/ w ack subaddress ack data ack stop sdata sclock 1 7 figure 53. bus data transfer figure 53 illustrates an example of data transfer for a read sequence and the start and stop conditions. figure 54 shows bus write and read sequences.
ADV7192 C29C rev. 0 register accesses the mpu can write to or read from all of the registers of the ADV7192 with the exception of the subaddress reg isters which are write only registers. the subaddress register determines which register the next read or write operation accesses. all com- munications with the part through the bus start with an access to the subaddress register. then a read/write operation is per- formed fr om/to the target address which then increments to the next address until a stop command on the bus is per formed. register programming the following section describes each register. all registers can be read from as well as written to. address sr6 sr5 sr4 sr3 sr2 sr1 sr0 00h 0 0 0 0 0 0 0 mode register 0 01h 0 0 0 0 0 0 1 mode register 1 02h 0 0 0 0 0 1 0 mode register 2 03h 0 0 0 0 0 1 1 mode register 3 04h 0 0 0 0 1 0 0 mode register 4 05h 0 0 0 0 1 0 1 mode register 5 06h 0 0 0 0 1 1 0 mode register 6 07h 0 0 0 0 1 1 1 mode register 7 08h 0 0 0 1 0 0 0 mode register 8 09h 0 0 0 1 0 0 1 mode register 9 0ah 0 0 0 1 0 1 0 timing register 0 0bh 0 0 0 1 0 1 1 timing register 1 0ch 0 0 0 1 1 0 0 subcarrier frequency register 0 0dh 0 0 0 1 1 0 1 subcarrier frequency register 1 0eh 0 0 0 1 1 1 0 subcarrier frequency register 2 0fh 0 0 0 1 1 1 1 subcarrier frequency register 3 10h 0 0 1 0 0 0 0 subcarrier phase register 11h 0 0 1 0 0 0 1 closed captioning extended data byte 0 12h 0 0 1 0 0 1 0 closed captioning extended data byte 1 13h 0 0 1 0 0 1 1 closed captioning data byte 0 14h 0 0 1 0 1 0 0 closed captioning data byte 1 15h 0 0 1 0 1 0 1 ntsc pedestal/teletext control register 0 16h 0 0 1 0 1 1 0 ntsc pedestal/teletext control register 1 17h 0 0 1 0 1 1 1 ntsc pedestal/teletext control register 2 18h 0 0 1 1 0 0 0 ntsc pedestal/teletext control register 3 19h 0 0 1 1 0 0 1 cgms/wss 0 1ah 0 0 1 1 0 1 0 cgms/wss 1 1bh 0 0 1 1 0 1 1 cgms/wss 2 1ch 0 0 1 1 1 0 0 teletext request control register 1dh 0 0 1 1 1 0 1 contrast control register 1eh 0 0 1 1 1 1 0 u scale register 1fh 0 0 1 1 1 1 1 v scale register 20h 0 1 0 0 0 0 0 hue adjust control register 21h 0 1 0 0 0 0 1 brightness control register 22h 0 1 0 0 0 1 0 sharpness response register 23h 0 1 0 0 0 1 1 dnr register 0 24h 0 1 0 0 1 0 0 dnr register 1 25h 0 1 0 0 1 0 1 dnr register 2 26h 0 1 0 0 1 1 0 gamma correction register 0 27h 0 1 0 0 1 1 1 gamma correction register 1 28h 0 1 0 1 0 0 0 gamma correction register 2 29h 0 1 0 1 0 0 1 gamma correction register 3 2ah 0 1 0 1 0 1 0 gamma correction register 4 2bh 0 1 0 1 0 1 1 gamma correction register 5 2ch 0 1 0 1 1 0 0 gamma correction register 6 2dh 0 1 0 1 1 0 1 gamma correction register 7 2eh 0 1 0 1 1 1 0 gamma correction register 8 2fh 0 1 0 1 1 1 1 gamma correction register 9 30h 0 1 1 0 0 0 0 gamma correction register 10 31h 0 1 1 0 0 0 1 gamma correction register 11 32h 0 1 1 0 0 1 0 gamma correction register 12 33h 0 1 1 0 0 1 1 gamma correction register 13 34h 0 1 1 0 1 0 0 brightness detect register 35h 0 1 1 0 1 0 1 output clock register 36h 0 1 1 0 1 1 0 reserved 37h 0 1 1 0 1 1 1 reserved 38h 0 1 1 1 0 0 0 reserved 39h 0 1 1 1 0 0 1 reserved 3ah 0 1 1 1 0 1 0 macrovision register 3bh 0 1 1 1 0 1 1 macrovision register 3ch 0 1 1 1 1 0 0 macrovision register 3dh 0 1 1 1 1 0 1 macrovision register 3eh 0 1 1 1 1 1 0 macrovision register 3fh 1 1 1 1 1 1 1 macrovision register 40h 1 0 0 0 0 0 0 macrovision register 41h 1 0 0 0 0 0 1 macrovision register 42h 1 0 0 0 0 1 0 macrovision register 43h 1 0 0 0 0 1 1 macrovision register 44h 1 0 0 0 1 0 0 macrovision register 45h 1 0 0 0 1 0 1 macrovision register 46h 1 0 0 0 1 1 0 macrovision register 47h 1 0 0 1 1 1 1 macrovision register 48h 1 0 0 1 0 1 0 macrovision register 49h 1 0 0 1 0 0 1 macrovision register 4ah 1 0 0 1 0 0 0 macrovision register 4bh 1 0 0 1 0 1 1 macrovision register ADV7192 subaddress register sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sr7 zero should be written here figure 55. subaddress register for the ADV7192 subaddress register (sr7?r0) the communications register is an eight bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 55 shows the various operations under the control of the subaddress register 0 should always be written to sr7. register select (sr6?r0) these bits are set up to point to the required starting address.
ADV7192 C30C rev. 0 mode register 0 mr0 (mr07?r00) (address (sr4?r0) = 00h) figure 56 shows the various operations under the control of mode register 0. mr0 bit description output video standard selection control (mr00?r01) these bits are used to set up the encoder mode. the ADV7192 can be set up to output ntsc, pal (b, d, g, h, i), pal m or pal n standard video. luminance filter select (mr02?r04) these bits specify which luma ?ter is to be selected. the ?ter selection is made independent of whether pal or ntsc is selected. chrominance filter select (mr05?r07) these bits select the chrominance ?ter. a low-pass ?ter can be selected with a choice of cutoff frequencies (0.65 mhz, 1.0 mhz, 1.3 mhz, 2 mhz, or 3 mhz) along with a choice of cif or qcif ?ters. mode register 1 mr1 (mr17?r10) (address (sr4?r0) = 01h) figure 57 shows the various operations under the control of mode register 1. mr1 bit description dac control (mr10?r15) bits mr15?r10 can be used to power-down the dacs. this are used to reduce the power consumption of the ADV7192 or if any of the dacs are not required in the application. 4 oversampling control (mr16) to enable 4 oversampling this bit has to be set to 1. when enabled, the data is output at a frequency of 54 mhz. note that pll enable control has to be enabled (mr61 = 0) in 4 oversampling mode. an external v ref is not recommended in that mode. reserved (mr17) a logical 0 must be written to this bit. mr07 mr06 mr05 mr04 mr03 mr02 mr01 mr00 chroma filter select 0 0 0 1.3 mhz low-pass filter 0 0 1 0.65 mhz low-pass filter 0 1 0 1.0 mhz low-pass filter 0 1 1 2.0 mhz low-pass filter 1 0 0 reserved 1 0 1 cif 1 1 0 qcif 1 1 1 3.0 mhz low-pass filter mr07 mr06 mr05 mr04 mr03 mr02 luma filter select 0 0 0 low-pass filter (ntsc) 0 0 1 low-pass filter (pal) 0 1 0 notch filter (ntsc) 0 1 1 notch filter (pal) 1 0 0 extended mode 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr01 mr00 0 0 ntsc 0 1 pal (b, d, g, h, i) 1 0 pal (m) 1 1 pal (n) output video standard selection figure 56. mode register 0, mr0 mr17 mr16 mr15 mr14 mr13 mr12 mr11 mr10 dac a dac control 0 power-down 1 normal mr15 dac c dac control 0 power-down 1 normal mr13 dac e dac control 0 power-down 1 normal mr11 4 oversampling control 02 oversampling 14 oversampling mr16 dac b dac control 0 power-down 1 normal mr14 dac d dac control 0 power-down 1 normal mr12 dac f dac control 0 power-down 1 normal mr10 mr17 zero must be written to this bit figure 57. mode register 1, mr1
ADV7192 C31C rev. 0 mode register 2 mr2 (mr27?r20) (address (sr4?r0) = 02h) mode register 2 is an 8-bit-wide register. figure 58 shows the various operations under the control of mode register 2. mr2 bit descriptionrgb/yuv control (mr20) this bit enables the output from the dacs to be set to yuv or rgb output video standard. dac output control (mr21) this bit controls the output from dacs a, b, and c. when this bit is set to 1, composite, luma and chroma signals are output from dacs a, b, and c (respectively). when this bit is set to 0, rgb or yuv may be output from these dacs. scart enable control (mr22) this bit is used to switch the dac outputs from scart to a euroscart con?uration. a complete table of all dac out- put con?urations is shown below. pedestal control (mr23) this bit speci?s whether a pedestal is to be generated on the ntsc composite video signal. this bit is invalid when the de vice is con?ured in pal mode. square pixel control (mr24) this bit is used to set up square pixel mode. this is available in slave mode only. for ntsc, a 24.54 mhz clock must be sup- plied. for pal, a 29.5 mhz clock must be supplied. square pixel operation is not available in 4 oversampling mode. standard i 2 c control (mr25) this bit controls the video standard used by the ADV7192. when this bit is set to 1 the video standard is as pro grammed in mode register 0 (output video standard selection). w hen it is set to 0, the ADV7192 is forced into the standard selected by the ntsc_pal pin. when ntsc_pal is low, the standard is ntsc, when the ntsc_pal pin is high, the standard is pal. pixel data valid control (mr26) after resetting the device this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is output from the dacs. the ADV7192 will be set to master mode timing. when this bit is set to 1 by the user (via the i 2 c), pixel data passes to the pins and the encoder reverts to the timing mode de?ed by timing register 0. sleep mode control (mr27) when this bit is set (1), sleep mode is enabled. with this mode enabled, the ADV7192 current consumption is reduced to typi- cally 0.1 a. the i 2 c registers can be written to and read from when the ADV7192 is in sleep mode. when the device is in sleep mode and 0 is written to mr27, the ADV7192 will come out of sleep mode and resume normal operation. also, if a reset is applied during sleep mode the ADV7192 will come out of sleep mode and resume normal operation. for this to operate power up in sleep mode control has to be enabled (mr60 is set to a logic 0), otherwise sleep mode is controlled by the pal_ntsc and screset/rtc/tr pins. mr27 mr26 mr25 mr24 mr23 mr22 mr21 mr20 rgb/yuv control 0 rgb output 1 yuv output mr20 scart enable control 0 disable 1 enable mr22 square pixel control 0 disable 1 enable mr24 pixel data valid control 0 disable 1 enable mr26 dac output control 0 rgb/yuv/comp 1 comp/luma/chroma mr21 pedestal control 0 pedestal off 1 pedestal on mr23 standard i 2 c control 0 disable 1 enable mr25 sleep mode control 0 disable 1 enable mr27 figure 58. mode register 2, mr2 table iii. dac output con?uration mr22 mr21 mr20 dac a dac b dac c dac d dac e dac f 0 0 0 g (y) b (pb) r (pr) cvbs luma chroma 0 0 1 y (y) u (pb) v (pr) cvbs luma chroma 0 1 0 cvbs luma chroma g (y) b (pb) r (pr) 0 1 1 cvbs luma chroma y (y) u (pb) v (pr) 1 0 0 cvbs b (pb) r (pr) g (y) luma chroma 1 0 1 cvbs u (pb) v (pr) y (y) luma chroma 1 1 0 cvbs luma chroma g (y) b (pb) r (pr) 1 1 1 cvbs luma chroma y (y) u (pb) v (pr) note in progressive scan mode (mr80 = 1) the dac output con?uration is stated in the brackets.
ADV7192 C32C rev. 0 mode register 3 mr3 (mr37?r30) (address (sr4?r0) = 03h) mode register 3 is an 8-bit-wide register. figure 59 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr30?r31) this bit is read only and indicates the revision of the device. vbi open (mr32) this bit determines whether or not data in the vertical blanking interval (vbi) is output to the analog outputs or blanked. note that this condition is also valid in timing slave mode 0. for further information see vertical blanking data insertion and blank input section. teletext enable (mr33) this bit must be set to 1 to enable teletext data insertion on the ttx pin. note: ttx functionality is shared with vso and clamp on pin 62. clamp/ vso select (mr77) and ttx input/clamp vso output (mr76) have to be set accord ingly. teletext bit request mode control (mr34) this bit enables switching of the teletext request signal from a continuous high signal (mr34 = 0) to a bitwise request signal (mr34 = 1). closed captioning field selection (mr35?r36) these bits control the ?lds that closed captioning data is dis- played on, closed captioning information can be displayed on an odd ?ld, even ?ld or both ?lds. reserved (mr37) a logic 0 must be written to this bit. mode register 4 mr4 (mr47?r40) (address (sr4?r0) = 04h) mode register 4 is an 8-bit-wide register. figure 60 shows the various operations under the control of mode register 4. mr4 bit description vsync_3h control (mr40) when this bit is enabled (1) in slave mode, it is possible to drive the vsync input low for 2.5 lines in pal mode and three lines in ntsc mode. when this bit is enabled in master mode the ADV7192 outputs an active low vsync signal for three lines in ntsc mode and 2.5 lines in pal mode. genlock control (mr41?r42) these bits control the genlock feature and timing reset of the ADV7192. setting mr41 and mr42 to logic 0 disables the screset/rtc/tr pin and allows the ADV7192 to operate in normal mode. 1. by setting mr41 to zero and mr42 to one, a timing reset is applied, resetting the horizontal and vertical counters. this has the effect of resetting the field count to field 0. if the screset/rtc/tr pin is held high, the counters will remain reset. once the pin is released the counters will commence counting again. for correct counter reset, the screset/rtc/tr pin has to remain high for at least 37 ns (one clock cycle at 27 mhz). 2. if mr41 is set to one and mr42 is set to zero, the sc reset/ rtc/tr pin is con?ured as a subcarrier reset input and the subcarrier phase will reset to field 0 whenever a low-to- high transition is detected on the screset/rtc/tr pin (sch phase resets at the start of the next ?ld). 3. if mr41 is set to one and mr42 is set to one, the screset/ rtc/tr pin is con?ured as a real time control input and the ADV7192 can be used to lock to an exte rnal video source working in rtc mode. see real-time control, subcarrier reset and timing reset section. active video line duration (mr43) this bit switches between two active video line durations. a zero sele cts ccir rec. 601 (720 pixels pal/ntsc) and a one selects itu-r bt. 470 standard for active video duration (710 pixels ntsc, 702 pixels pal). chrominance control (mr44) this bit enables the color information to be switched on and off the chroma, composite and color component outputs. burst control (mr45) this bit enables the color burst to be switched on and off the chroma and composite outputs. color bar control (mr46) this bit can be used to generate and output an internal color bar test pattern. the color bar con?uration is 100/7.5/75/7.5 for ntsc and 100/0/75/0 for pal. it is important to note that when color bars are enabled the ADV7192 is con?ured in a master timing mode. the output pins vsync , hsync and blank are three-state during color bar mode. interlaced mode control (mr47) this bit is used to setup the output to interlaced or noninterlaced mode. mr37 zero must be written to this bit mr37 mr36 mr35 mr34 mr33 mr32 mr31 mr30 mr31 mr30 reserved for revision code vbi open 0 disable 1 enable mr32 ttx bit request mode control 0 disable 1 enable mr34 teletext enable 0 disable 1 enable mr33 closed captioning field selection mr36 mr35 0 0 no data out 0 1 odd field only 1 0 even field only 1 1 data out (both fields) figure 59. mode register 3, mr3
ADV7192 C33C rev. 0 mode register 5 mr5 (mr57?r50) (address (sr4?r0) = 05h) mode register 5 is a 8-bit-wide register. figure 61 shows the various operations under the control of mode register 5. mr5 bit description y-level control (mr50) this bit controls the component y output level on the ADV7192 if this bit is set (0), the encoder outputs betacam lev els when con?ured in pal or ntsc mode. if this bit is set (1), the encoder outputs smpte levels when con?ured in pal or ntsc mode. uv-levels control (mr51?r52) these bits control the component u and v output levels on the ADV7192. it is possible to have uv levels with a peak-to-peak amplitude of either 700 mv (mr52 + mr51 = 01) or 1000 mv (mr52 + mr51 = 10) in ntsc and pal. it is also p ossible to have default values of 934 mv for ntsc and 700 mv for pal (mr52 + mr51 = 00). rgb sync (mr53) this bit is used to set up the rgb outputs with the sync infor- mation encoded on all rgb outputs. clamp delay (mr54?r55) these bits control the delay or advance of the clamp signal in the front or back porch of the ADV7192. it is possible to delay or advance the pulse by zero, one, two or three clock cycles. note: ttx functionality is shared with vso and clamp on pin 62. clamp/ vso select (mr77) and ttx input/clamp vso output (mr76) have to be set accordingly. clamp delay direction (mr56) this bit controls a positive or negative delay in the clamp sig- nal. if this bit is set (1), the delay is negative. if it is set (0), the delay is positive. clamp position (mr57) this bit controls the position of the clamp signal. if this bit is set (1), the clamp signal is located in the back porch position. if this bit is set (0), the clamp signal is located in the front porch position. mr57 mr56 mr55 mr54 mr53 mr52 mr51 mr50 0 positive 1 negative mr56 clamp delay direction uv level control mr52 mr51 0 0 default levels 0 1 700mv 1 0 1000mv 1 1 reserved 0 disable 1 enable mr53 rgb sync clamp position 0 front porch 1 back porch mr57 0 disable 1 enable mr50 y level control clamp delay mr55 mr54 0 0 no delay 011 pclk 102 pclk 113 pclk figure 61. mode register 5, mr5 mr47 mr46 mr45 mr44 mr43 mr42 mr41 mr40 0 disable 1 enable mr46 color bar control chrominance control 0 enable color 1 disable color mr44 genlock control mr42 mr41 0 0 disable genlock 0 1 enable subcarrier reset pin 1 0 timing reset 1 1 enable rtc pin 0 disable 1 enable mr40 vsync 3h control burst control 0 enable burst 1 disable burst mr45 active video line duration 0 720 pixels 1 710 pixels/702 pixels mr43 interlace mode control 0 interlaced 1 noninterlaced mr47 figure 60. mode register 4, mr4
ADV7192 C34C rev. 0 mode register 6 mr6 (mr67?r60) (address (sr4?r0) = 06h) mode register 6 is a 8-bit-wide register. figure 62 shows the various operations under the control of mode register 6. mr6 bit description power-up sleep mode control (mr60) after reset is applied this control is enabled (mr60 = 0) if both screset/rtc/tr and ntsc_pal pins are tied high. the ADV7192 will then power up in sleep mode to facilitate low power consumption before the i 2 c is initialized. when this control is disabled (mr60 = 1, via the i 2 c) sleep mode control passes to sleep mode control, mr27. ppl enable control (mr61) the pll control should be enabled (mr61 = 0 ) when 4 oversampling is enabled (mr16 = 1). when this bit is toggled, it is also used to reset the pll. reserved (mr62, mr63, mr64) a logical 0 must be written to these bits. field counter (mr65, mr66, mr67) these three bits are read only bits. the ?ld count can be read back over the i 2 c interface. in ntsc mode the ?ld count goes from 0?, in pal mode from 0?. mode register 7 mr7 (mr77?r70) (address (sr4?r0) = 07h) mode register 7 is a 8-bit-wide register. figure 63 shows the various operations under the control of mode register 7. mr7 bit description color control enable (mr70) this bit is used to enable control of contrast and saturation of color. if this bit is set (1) color controls are enabled (contrast control register, u-scale register, v-scale register). if this bit is set (0), the color control features are disabled. luma saturation control (mr71) when this bit is set (1), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 (after scaling by the contrast control register). this prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. when this bit is set (0), this control is disabled. hue adjust control (mr72) this bit is used to enable hue adjustment on the composite and chroma output signals of the ADV7192. when this bit is set (1), the hue of the color is adjusted by the phase offset described in the hue adjust control register. when this bit is set (0), hue adjustment is disabled. brightness enable control (mr73) this bit is used to enable brightness control on the ADV7192. the actual brightness level is programmed in the b rightness control register. this value or set-up level is added to the scaled y data. when this bit is set (1), brightness control is enabled. when this bit is set (0), brightness control is disabled. sharpness filter enable (mr74) this bit is used to enable the sharpness control of the luminance signal on the ADV7192 (luma filter select has to be set to ex- tended, mr04?r02 = 100). the various re sponses of the ?ter are determined by the sharpness control register. when this bit is set (1), the luma response is altered by the amount d escribed in the sharpness control register. when this bit is set (0), the sharpness control is disabled. see internal filter response section for luma signal responses. cso_hso output control (mr75) this bit is u sed to determine whether hso or cso ttl output signal is output at the cso_hso pin. if this bit is set (1), the cso ttl signal is output. if this bit is set (0), the hso ttl signal is output. ttx input/clamp vso output (mr76) this bit controls whether pin 62 is con?ured as an output or as an input pin. a 1 selects pin 62 to be an output for clamp or vso functionality. a 0 selects this pin as a ttx input pin. mr77 mr76 mr75 mr74 mr73 mr72 mr71 mr70 0 disable 1 enable mr74 sharpness filter enable 0 vso output 1 clamp output mr77 clamp/ vso select 0 disable 1 enable mr70 color control enable cso_hso output control 0 hso out 1 cso out mr75 0 disable 1 enable mr72 hue adjust control 0 disable 1 enable mr73 brightness enable control 0 disable 1 enable mr71 luma saturation control mr76 ttx input/clampC vso output control 0 ttx input 1 clamp/ vso output figure 63. mode register 7, mr7 mr67 mr66 mr65 mr64 mr63 mr62 mr61 mr60 0 enabled 1 disabled mr60 power-up sleep mode control 0 enabled 1 disabled mr61 pll enable control zero must be written to these bits mr64 mr63 mr62 field counter mr67 mr66 mr65 figure 62. mode register 6, mr6
ADV7192 C35C rev. 0 clamp/ vso select (mr77) this bit is used to select the functionality of pin 62. setting this bit to 1 selects clamp as the output signal. a 0 selects vso as the output signal. since this pin is also shared with the ttx functionality, ttx input/clamp vso output has to be set accordingly (mr76). mode register 8 mr8 (mr87?r80) (address (sr4?r0) = 08h) mode register 8 is an 8-bit-wide register. figure 64 shows the various operations under the control of mode register 8. mr8 bit description progressive scan control (mr80) this control enables the progressive scan inputs on pins y(0)/p8y (7)/p15, y(8)?(9), cr(0)?r(9), cb(0)?b(9) . to enable this control mr80 has to be set to 1. it is assumed that the incoming y data contains all necessary sync information. note: simultaneous pro gressive scan input and 16-bit pixel input is not possible. reserved (mr81) a 0 must be written to this bit. double buffer control (mr82) double buffering can be enabled or disabled on the contrast control register, u scale register, v scale register, hue a djust control register, closed captioning register, brightness control register, gamma c urve select bit and the macrovision regis- ters. double buffer is not available in master mode. 16-bit pixel port (mr83) this bit controls if the ADV7192 is operated in 8-bit or 16-bit mode. in 8-bit mode the input data will be set up on pins p0p7. reserved (mr84) a logic 0 must be written to this bit. dnr enable control (mr85) to enable the dnr process this bit has to be set to 1. if this bit is set to other dnr processing is bypassed. for further informa- tion on dnr controls see dnr mode control section. gamma enable control (mr86) to enable the programmable gamma correction this bit has to be set to enabled (mr86 = 1). for further information on gamma correction controls see gamma correction registers section. gamma curve select control (mr87) this bit selects which of the two programmable gamma curves is to be used. when setting mr87 to 0, the gamma correction c urve selected is curve a. otherwise, curve b is selected. each curve will have to be programmed by the user. for further information on gamma correction controls see gamma correction regis- ters section. mode register 9 mr9 (mr97?r90) (address (sr4?r0) = 09h) mode register 9 is an 8-bit-wide register. figure 66 shows the various operations under the control of mode register 9. mr9 bit description undershoot limiter (mr90?r91) this control ensures that no luma video data will go below a programmable level. this prevents any synchronization problems due to luma signals going below the blanking level. available limit levels are ?.5 ire, ? ire, ?1 ire. note that this facility is only available in 4 oversampling mode (mr16 = 1). when the device is operated in 2 oversampling mode (mr16 = 0) or rgb output without rgb sync are selected, the minimum luma level is set in timing register 0, tr06 (min luma c ontrol). black burst y dac (mr92) it is possible to output a black burst signal from the dac which is selected to be the luma dac (mr22, mr21, mr20). this signal can be useful for locking two video sources together using professional video equipment. see also black burst out- put section. black burst luma (mr93) it is possible to output a black burst signal from the dac which is selected to be the y-dac (mr22, mr21, mr20). this signal can be useful for locking two video sources together using pro- fessional video equipment. see also black burst output section. 20 ire 0 ire C20 ire C40 ire 21.5 ire 0 ire C21.5 ire C43 ire 3.58mhz color burst (9 cycles) 4.43mhz color burst (10 cycles) ntsc black burst signal pal black burst signal figure 65. black burst signals for pal and ntsc standards zero should be written to this bit mr84 mr87 mr86 mr85 mr84 mr83 mr82 mr81 mr80 mr83 16-pixel port control 0 disable 1 enable dnr enable control mr85 0 disable 1 enable 0 disable 1 enable mr82 double buffer control 0 disable 1 enable mr86 gamma enable control 0 curve a 1 curve b mr87 gamma curve select control zero should be written to this bit mr81 0 disable 1 enable mr80 progressive scan control figure 64. mode register 8, mr8
ADV7192 C36C rev. 0 chroma delay control (mr94?r95) the chroma signal can be delayed by up to 8 clock cycles at 27 mhz using mr94?5. for further information see also chroma/luma delay section. timing register 0 (tr07?r00) (address (sr4?r0) = 0ah) figure 67 shows the various operations under the control of timing register 0. this register can be read from as well as written to. tr0 bit description master/slave control (tr00) this bit controls whether the ADV7192 is in master or slave mode. timing mode selection (tr01?r02) these bits control the timing mode of the ADV7192. these modes are described in more detail in the video timing de scrip- tion section of the data sheet. blank input control (tr03) this bit controls whether the blank input is used to accept blank signals or whether blank signals are internally generated. note: when this input pin is tied high (to 5 v), the input is dis- abled regardless of the register setting. it, therefore, should be tied low (to ground) to allow control over the i 2 c register. luma delay (tr04?r05) the luma signal can be delayed by up to 222 ns (or six clock cycles at 27 mhz) using tr04?r05. for further information see chroma/luma delay section. min luminance value (tr06) this bit is used to control the minimum luma output value by the ADV7192 in 2 oversampling mode and 4 oversam pling mode. when this bit is set to a logic 1, the luma is lim ited to 7ire below the blank level. when this bit is set to (0), the luma value can be as low as the sync bottom level. timing register reset (tr07) toggling tr07 from low to high and low again resets the inter- nal timing counters. this bit should be toggled after power-up, reset or changing to a new timing mode. timing register 1 (tr17?r10) (address (sr4?r0) = 0bh) timing register 1 is a 8-bit-wide register. figure 68 shows the various operations under the control of timing register 1. this register can be read from as well written to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync width (tr10?r11) these bits adjust the hsync pulsewidth. t pclk = one clock cycle at 27 mhz. hsync to vsync delay (tr13?r12) these bits adjust the position of the hsync output relative to the vsync output. t pclk = one clock cycle at 27 mhz. hsync to vsync rising edge delay (tr14?r15) when the ADV7192 is in timing mode 1, these bits adjust the position of the hsync output relative to the vsync output rising edge. t pclk = one clock cycle at 27 mhz. vsync width (tr14?r15) when the ADV7192 is con?ured in timing mode 2, these bits adjust the vsync pulsewidth. t pclk = one clock cycle at 27 mhz. hsync to pixel data adjust (tr16?r17) this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. mr97 mr96 mr95 mr94 mr93 mr92 mr91 mr90 zero must be written to these bits mr97 mr96 chroma delay control mr95 mr94 0 0 0ns delay 0 1 148ns delay 1 0 296ns delay 1 1 reserved undershoot limiter mr91 mr90 0 0 disabled 0 1 C11 ire 1 0 C6 ire 1 1 C1.5 ire 0 disable 1 enable mr93 black burst luma dac black burst y dac 0 disable 1 enable mr92 figure 66. mode register 9 (mr9) tr07 tr06 tr05 tr04 tr03 tr02 tr01 tr00 0 luma min = sync bottom 1 luma min = blank C7.5 ire tr06 min luminance value 0 enable 1 disable tr03 blank input control timing register reset tr07 0 slave timing 1 master timing tr00 master / slave control luma delay tr05 tr04 0 0 0ns delay 0 1 74ns delay 1 0 148ns delay 1 1 222ns delay tr02 tr01 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 timing mode selection figure 67. timing register 0
ADV7192 C37C rev. 0 this adjustment is available in both master and slave timing modes. t pclk = one clock cycle at 27 mhz. subcarrier frequency registers 3? (fsc31?sc0) (address (sr4?r0) = 0ch?fh) these 8-bit-wide registers are used to set up the subcarrier fre- quency. the value of these registers are calculated by using the following equation: subcarrier frequency f f scf clk register = () 21 32 example : ntsc mode, f clk = 27 mhz , f scf = 3.5795454 mhz subcarrier frequency alue v = () 2 1 3 5795454 10 27 10 32 6 6 . subcarrier register value = 21f07c16 hex figure 69 shows how the frequency is set up by the four registers. fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 subcarrier frequency reg 3 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier frequency reg 2 subcarrier frequency reg 1 fsc7 fsc6 fsc5 fsc4 fsc3 fsc2 fsc1 fsc0 subcarrier frequency reg 0 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc9 fsc8 figure 69. subcarrier frequency registers subcarrier phase register (fph7?ph0) (address (sr4?r0) = 10h) this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41 . for normal operation this register is set to 00hex. fph7 fph6 fph5 fph4 fph3 fph2 fph1 fph0 subcarrier phase register figure 70. subcarrier phase register closed captioning even field data register 1? (ccd15?cd0) (address (sr4?r0) = 11?2h) these 8-bit-wide registers are used to set up the closed captio ning extended data bytes on even fields. figure 71 shows how the high and low bytes are set up in the registers. ccd15 ccd14 ccd13 ccd12 ccd11 ccd10 ccd9 ccd8 byte 1 ccd7 ccd6 ccd5 ccd4 ccd3 ccd2 ccd1 ccd0 byte 0 figure 71. closed captioning extended data register closed captioning odd field data register 1? (ced15-ced0) (subaddress (sr4?r0) = 13?4h) these 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. figure 72 shows how the high and low bytes are set up in the registers. ced15 ced14 ced13 ced12 ced11 ced10 ced9 ced8 byte 1 ced7 ced6 ced5 ced4 ced3 ced2 ced1 ced0 byte 0 figure 72. closed captioning data register ntsc pedestal/pal teletext control registers 3? (pce15?, pco15?)/(txe15?, txo15?) (subaddress (sr4?r0) = 15?8h) these 8-bit-wide registers are used to enable the ntsc pedestal/ pal teletext on a line-by-line basis in the vertical blanking interval for both odd and even elds. figures 73 and 74 show the four control registers. a logic 1 in any of the bits of these tr17 tr16 tr15 tr14 tr13 tr12 tr11 tr10 tr17 tr16 0 0 0 t pclk 011 t pclk 102 t pclk 113 t pclk hsync to pixel data adjust tr15 tr14 t c 0 t b 1t b + 32 s hsync to vsync rising edge delay (mode 1 only) tr13 tr12 t b 0 0 0 t pclk 014 t pclk 108 t pclk 1 1 18 t pclk hsync to vsync delay tr11 tr10 t a 0 0 1 t pclk 014 t pclk 1 0 16 t pclk 1 1 128 t pclk hsync width tr15 tr14 0 0 1 t pclk 014 t pclk 1 0 16 t pclk 1 1 128 t pclk vsync width (mode 2 only) line 313 line 314 line 1 t b t a t c vsync hsync timing mode 1 (master/pal) figure 68. timing register 1
ADV7192 C38C rev. 0 registers has the effect of turning the pedestal off on the equiva- lent line when used in ntsc. a logic 1 in any of the bits of these registers has the effect of turning teletext on on the equivalent line when used in pal. pco7 pco6 pco5 pco4 pco3 pco2 pco1 pco0 field 1/3 pco15 pco14 pco13 pco12 pco11 pco10 pco9 pco8 field 1/3 pce15 pce14 pce13 pce12 pce11 pce10 pce9 pce8 pce7 pce6 pce5 pce4 pce3 pce2 pce1 pce0 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 2/4 field 2/4 figure 73. pedestal control registers txo7 txo6 txo5 txo4 txo3 txo2 txo1 txo0 field 1/3 txo15 txo14 txo13 txo12 txo11 txo10 txo9 txo8 field 1/3 txe15 txe14 txe13 txe12 txe11 txe10 txe9 txe8 txe7 txe6 txe5 txe4 txe3 txe2 txe1 txe0 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 field 2/4 field 2/4 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 figure 74. teletext control registers teletext request control register tc07 (tc07?c00) (address (sr4?r0) = 1ch) teletext c ontrol r egister is an 8-bit-wide register. see figure 75. ttxreq falling edge control (tc00?c03) these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a maximum of 15 clock cycles. this controls the active window for teletext data. increasing t his value reduces the amount of teletext bits below the default of 360. if bits tc00 tc03 are 00hex when bits tc04 tc07 are changed then the falling edge of ttreq will track that of the rising edge (i.e., the time between the falling and rising edge remains constant). pclk = clock cycle at 27 mhz. ttxreq rising edge control (tc04?c07) these bits control the position of the rising edge of ttxreq. it can be programmed from zero clock cycles to a maximum of 15 clock cycles. pclk = clock cycle at 27 mhz. tc07 tc06 tc05 tc04 tc03 tc02 tc01 tc00 tc03 tc02 tc01 tc00 0 0 0 0 0 pclk 0 0 0 1 1 pclk '' '' '' '' '' pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk ttxreq falling edge control tc07 tc06 tc05 tc04 0 0 0 0 0 pclk 0 0 0 1 1 pclk '' '' '' '' '' pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk ttxreq rising edge control figure 75. teletext control register cgms_wss register 0 c/w0 (c/w07?/w00) (address (sr4?r0) = 19h) cgms_wss register 0 is an 8-bit-wide register. figure 76 shows the operations under control of this register. c/w0 bit description cgms data bits (c/w00?/w03) these four data bits are the nal four bits of cgms data out- put stream. note it is cgms data only in these bit positions, i.e., wss data does not share this location. cgms crc check control (c/w04) when this bit is enabled (1), the last six bits of the cgms data, i.e., the crc check sequence, is internally calculated by the ADV7192. if this bit is disabled (0) the crc values in the reg- ister are output to the cgms data stream. cgms odd field control (c/w05) when this bit is set (1), cgms is enabled for odd elds. note this is only valid in ntsc mode. cgms even field control (c/w06) when this bit is set (1), cgms is enabled for even elds. note this is only valid in ntsc mode. wss control (c/w07) when this bit is set (1), wide screen signalling is enabled. note this is only valid in pal mode. cgms_wss register 1 c/w1 (c/w17?/w10) (address (sr4?r0) = 1ah) cgms_wss register 1 is an 8-bit-wide register. figure 77 shows the operations under control of this register. c/w1 bit description cgms/wss data (c/w10?/w15) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 0 disable 1 enable c/w07 wss control 0 disable 1 enable c/w05 cgms odd field control 0 disable 1 enable c/w06 cgms even field control 0 disable 1 enable c/w04 cgms crc check control c/w03 C c/w00 cgms data bits figure 76. cgms_wss register 0
ADV7192 C39C rev. 0 cgms data (c/w16?/w17) these bits are cgms data bits only. c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15 C c/w10 cgms/wss data c/w17 C c/w16 cgms data figure 77. cgms_wss register 1 cgms_wss register 2 c/w1 (c/w27?/w20) (address (sr4?r0) = 1bh) cgms_wss register 2 is an 8-bit-wide register. figure 78 shows the operations under control of this register. c/w2 bit description cgms/wss data (c/w20?/w27) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. c/w27 C c/w20 cgms/wss data c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 figure 78. cgms_wss register 2 contrast control register (cc00?c07) (address (sr4?r0) = 1dh) the contrast control register is an 8-bit-wide register used to scale the y output levels. figure 79 shows the operation under control of this register. y scale value (cc00?c07) these eight bits represent the value required to scale the y pixel data from 0.0 to 1.5 of its initial level. the value of these eight bits is calculated using the following equation: y scale value = scale factor 128 example: scale factor = 1.18 y scale value = 1.18 128 = 151.04 y scale value = 151 (rounded to the nearest integer) y scale value = 10010111 b y scale value = 97 h cc07 C cc00 y scale value cc07 cc06 cc05 cc04 cc03 cc02 cc01 cc00 figure 79. contrast control register color control registers 1? (cc1?c2) (address (sr4?r0) = 1eh?fh) the color control registers are 8-bit-wide registers used to scale the u and v output levels. figure 75 shows the operations under control of these registers. cc17 C cc10 u scale value cc17 cc16 cc15 cc14 cc13 cc12 cc11 cc10 cc27 C cc20 v scale value cc27 cc26 cc25 cc24 cc23 cc22 cc21 cc20 figure 80. color control registers cc1 bit description u scale value (cc10?c17) these eight bits represent the value required to scale the u level from 0.0 to 2.0 of its initial level. the value of these eight bits is calculated using the following equation: u scale value = scale factor 128 example: scale factor = 1.18 u scale value = 1.18 128 = 151.04 u scale value = 151 (rounded to the nearest integer) u scale value = 10010111 b u scale value = 97 h cc2 bit description v scale value (cc20?c27) these eight bits represent the value required to scale the v pixel data from 0.0 to 2.0 of its initial level. the value of these eight bits is calculated using the following equation: v scale value = scale factor 128 example: scale factor = 1.18 v scale value = 1.18 128 = 151.04 v scale value = 151 (rounded to the nearest integer) v scale value = 10010111 b v scale value = 97 h
ADV7192 C40C rev. 0 hue adjust control register (hcr) (address (sr5?r0) = 20h) the hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. figure 81 shows the operation under control of this register. hcr7 C hcr0 hue adjust value hcr7 hcr6 hcr5 hcr4 hcr3 hcr2 hcr1 hcr0 figure 81. hue control register hcr bit description hue adjust value (hcr0?cr7) these eight bits represent the value required to vary the hue of the vi deo data, i.e., the variance in p hase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. the ADV7192 provides a range of 22.5 incre- ments of 0.17578125 . for normal operation (zero ad justment), this register is set to 80hex. ffhex and 00hex represent the upper and lower limit (respectively) of adjustment attainable. hue adjust [ ] = 0.17578125 ( hcr d 128); for positive hue adjust value example: to adjust the hue by 4 write 97 h to the hue adjust control register: (4/0.17578125) + 128 = 151 d * = 97 h to adjust the hue by ( 4 ) write 69 h to the hue adjust control register: ( 4/0.17578125) + 128 = 105 d * = 69 h * rounded to the nearest integer. brightness control register (bcr) (address (sr5?r0) = 21h) the brightness control register is an 8-bit-wide register which allows brightness control. figure 82 shows the operation under control of this register. bcr bit description brightness value (bcr0?cr6) seven bits of this 8-bit-wide register are used to control the brightness level. the brightness is controlled by adding a pro- grammable setup level onto the scaled y data. this brightness level can be a positive or negative value. the programmable brightness levels in ntsc, without pedestal, and pal are max 15 ire and min 7.5 ire, in ntsc pedestal max 22.5 ire and min 0 ire. table iv. brightness control register value setup setup brightness level in level in setup control ntsc with ntsc no level in register pedestal pedestal pal value 22.5 ire 15 ire 15 ire 1e h 15 ire 7.5 ire 7.5 ire 0f h 7.5 ire 0 ire 0 ire 00 h 0 ire 7.5 ire 7.5 ire 71 h note values in the range from 3f h to 44 h might result in an invalid output signal. example 1. standard: ntsc with pedestal. to add 20 ire brightness level write 28 h into the brightness control register: [ brightness control register value ] h = [ ire value 2.015631 ] h = [ 20 2.015631 ] h = [ 40.31262 ] h = 28 h 2. standard: pal. to add 7 ire brightness level write 72 h into the brightness control register: [| ire value | 2.015631] = [7 2.015631] = [14.109417] = 0001110 b [0001110] into two? complement = 1110010 b = 72 h bcr6 C bcr0 brightness value bcr7 zero must be written to this bit bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 100 ire 0 ire +7.5 ire C7.5 ire ntsc without pedestal no setup value added positive setup value added write to brightness control register: 12 h negative setup value added write to brightness control register: 6e h figure 82. brightness control register
ADV7192 C41C rev. 0 sharpness response register (pr) (address (sr5?r0) = 22h) the sharpness response register is an 8-bit-wide register. the four msbs are set to 0. the four lsbs are written to in order to select a desired lter response. figure 83 shows the operation under control of this register. pr bit description sharpness response value (pr3?r0) these four bits are used to select the desired luma lter response. the option of twelve responses is given supporting a gain bo ost/ attenuation in the range 4 db to +4 db. the value 12 (1100) written to these four bits corresponds to a boost of +4 db while the value 0 (0000) corresponds to 4 db. for normal operation these four bits are set to 6 (0110). note: luma filter select has to be set to extended mode and sharpness filter control has to be enabled for settings in the sharpness control register to take effect (mr02 04 = 100; mr74 = 1). reserved (pr4?r7) a logical 0 must be written to these bits. pr3 C pr0 sharpness response value zero must be written to these bits pr7 C pr4 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 figure 83. sharpness response register dnr registers 2? (dnr2?nr0) (address (sr5?r0) = 23h?5h) the digital noise reduction registers are three 8-bit-wide register. they are used to control the dnr processing. see digital noise register section. coring gain border (dnr00?nr03) these four bits are assigned to the gain factor applied to border areas. in dnr mode the range of gain values is 0 1, in increments of 1/8. this factor is applied to the dnr lter output which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode the range of gain values is 0 0.5, in increments of 1/16. this factor is applied to the dnr lter output which lies above the threshold range. the result is added to the original signal. coring gain data (dnr04?nr07) these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode the range of gain values is 0 1, in increments of 1/8. this factor is applied to the dnr lter output which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode the range of gain values is 0 0.5, in increments of 1/16. this factor is applied to the dnr lter out- put which lies above the threshold range. the result is added to the original signal. figures 84 and 85 show the various operations under the con trol of dnr register 0. dnr07 dnr06 dnr05 dnr04 dnr03 dnr02 dnr01 dnr00 coring gain data dnr dnr dnr dnr 07 06 05 04 0 0 0 0 0001+ 1/16 0010+ 2/16 0011+ 3/16 0100+ 4/16 0101+ 5/16 0110+ 6/16 0111+ 7/16 1000+ 8/16 coring gain border dnr dnr dnr dnr 03 02 01 00 0 0 0 0 0001+ 1/16 0010+ 2/16 0011+ 3/16 0100+ 4/16 0101+ 5/16 0110+ 6/16 0111+ 7/16 1000+ 8/16 figure 84. dnr register 0 in dnr sharpness mode coring gain data dnr dnr dnr dnr 07 06 05 04 0 0 0 0 0 0001 C1/8 0010 C2/8 0011 C3/8 0100 C4/8 0101 C5/8 0110 C6/8 0111 C7/8 1000C1 coring gain border dnr dnr dnr dnr 03 02 01 00 0 0 0 0 0 0001 C1/8 0010 C2/8 0011 C3/8 0100 C4/8 0101 C5/8 0110 C6/8 0111 C7/8 1000C1 dnr07 dnr06 dnr05 dnr04 dnr03 dnr02 dnr01 dnr00 figure 85. dnr register 0 in dnr mode dnr1 bit description dnr threshold (dnr10?nr15) these six bits are used to de ne the threshold value in the range of 0 to 63. the range is an absolute value. border area (dnr16) in setting dnr16 to a logic 1 the block transition area can be de ned to consist of four pixels. if this bit is set to a logic 0 the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 mhz. block size control (dnr17) this bit is used to select the size of the data blocks to be processed (see figure 86). setting the block size control function to a l ogic 1 de nes a 16 16 pixel data block, a logic 0 de nes an 8 8 pixel data block, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (ntsc) 2 pixel border data 8 8 pixel block 8 8 pixel block figure 86. mpeg block diagram
ADV7192 C42C rev. 0 dnr17 dnr16 dnr15 dnr14 dnr13 dnr12 dnr11 dnr10 dnr threshold dnr dnr dnr dnr dnr dnr 15 14 13 12 11 10 0 0 0 0 0 0 0 0000011 ??????? ??????? ??????? 11111062 11111163 0 2 pixels 1 4 pixels dnr16 border area 0 8 pixels 1 16 pixels dnr17 block size control figure 87. dnr register 1 dnr2 bit description dnr input select (dnr20?nr22) three bits are assigned to select the lter which is applied to the incoming y data. the signal which lies in the passband of the selected lter is the signal which will be dnr processed. figure 88 shows the lter responses selectable with this control. dnr mode control (dnr23) this bit controls the dnr mode selected. a logic 0 selects dnr mode, a logic 1 selects dnr sharpness mode. dnr works on the principle of de ning low amplitude, high- frequency signals as probable noise and subtracting this noise from the original signal. in dnr mode, it is possible to subtract a fraction of the signal which lies below the set threshold, assumed to be noise, from the original signal. the threshold is set in dnr register 1. when dnr sharpness mode is enabled it is possible to add a fraction of the signal which lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. the overall effect being that the signal will be boosted (similar to using extended ssaf filter). frequency C mhz 1 0.4 0.6 0.2 01 magnitude C db 234 6 5 0.8 0 filter d filter c filter b filter a figure 88. filter response of filters selectable filter output < threshold ? gain control block size control border area block offset gain coring gain data coring gain border filter block filter output > threshold dnr out main signal path y data input noise signal path subtract signal in threshold range from original signal dnr mode filter output > threshold ? gain control block size control border area block offset gain coring gain data coring gain border filter block filter output < threshold dnr out main signal path y data input noise signal path add signal above threshold range to original signal dnr sharpness mode figure 89. block diagram for dnr mode and dnr sharp- ness mode block offset (dnr24?nr27) four bits are assigned to this control which allows a shift of the data block of 15 pixels maximum. consider the coring gain positions xed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. o x x x x x x o o x x x x x x o apply data coring gain apply border coring gain dnr27-dnr24 = 01hex offset caused by variations in input timing o x x x x x x o o x x x x x x o o x x x x x x o o x x x x x x o figure 90. dnr27Cdnr24 block offset control
ADV7192 C43C rev. 0 gamma correction registers 0?3 (gamma correction 0?3) (address (sr5?r0) = 26h?2h) the gamma correction registers are fourteen 8-bit wide regis- ter. they are used to program the gamma correction curves a and b. generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the crt). it can also be applied wher- ever nonlinear processing is used. gamma correction uses the function: signal out = (s ignal in ) where = gamma power factor gamma correction is performed on the luma data only. the user has the choice to use two different curves, curve a or curve b. at any one time only one of these curves can be used. the response of the curve is programmed at seven prede ned locations. in changing the values at these locations the gamma curve can be modi ed. between these points linear interpolation is used to generate intermediate values. considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, and 224. location 0, 16, 240 and 255 are xed and can not be changed. for the length of 16 to 240 the gamma correction curve has to be calculated as below: y = x where y = gamma corrected output x = linear input signal = gamma power factor to program the gamma correction registers, the seven values for y have to be calculated using the following formula: y n = [ x (n 16) /(240 16) ] (240 16) + 16 where x (n -16) = value for x along x-axis at points n = 32, 64, 96, 128, 160, 192, or 224 y n = value for y along the y-axis, which has to be written into the gamma correction register example: y 32 = [(16/224) 0.5 224] + 16 = 76 * y 64 = [(48/224) 0.5 224] + 16 = 120 * y 96 = [(80/224) 0.5 224] + 16 = 150 * y 128 = [(112/224) 0.5 224] + 16 = 174 * * rounded to the nearest integer. the above will result in a gamma curve shown below, assuming a ramp signal as an input. 250 200 150 100 50 0 300 250 200 150 100 50 300 signal output signal input 0.5 gamma correction block output to a ramp input gamma-corrected amplitude 0 50 100 150 200 250 location figure 92. signal input (ramp) and signal output for gamma 0.5 250 200 150 100 50 0 300 signal outputs signal input 0.5 gamma correction block output to a ramp input for various gamma values gamma-corrected amplitude 0 50 100 150 200 250 location 0.3 1.5 1.8 figure 93. signal input (ramp) and selectable gamma output curves the gamma curves shown above are examples only, any user de ned curve is acceptable in the range of 16 240. dnr27 dnr26 dnr25 dnr24 dnr23 dnr22 dnr21 dnr20 block offset control dnr dnr dnr dnr 27 26 25 24 0000 0 pixel offset 0001 1 pixel offset 0010 2 pixel offset ???? ? ???? ? ???? ? 110113 pixel offset 111014 pixel offset 111115 pixel offset dnr input select control dnr dnr dnr 22 21 20 0 0 1 filter a 0 1 0 filter b 0 1 1 filter c 1 0 0 filter d 0 dnr mode 1 dnr sharpness mode dnr23 dnr mode control figure 91. dnr register 2
ADV7192 C44C rev. 0 ocr07 ocr06 ocr05 ocr04 ocr03 ocr02 ocr01 ocr00 ocr07 zero must be written to this bit clkout pin control 0 ensabled 1 disabled ocr01 ocr06 C ocr04 one must be written to these bits ocr03 C ocr02 zero must be written to these bits ocr00 zero must be written to this bit figure 94. output clock register brightness detect register (address (sr5?r0) = 34h) the brightness detect register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of the incom ing video data on a eld-by- eld basis. the bright ness information is read from the i 2 c and based on this information, the color controls or the gamma correction controls may be adjusted. the luma data is monitored in the active video area only. the average brightness i 2 c register is updated on the falling edge of every vsync signal. output clock register (ocr 9?) (address (sr4?r0) = 35h) the output clock register is an 8-bit-wide register. figure 93 shows the various operations under the control of this register. ocr bit description reserved (ocr00) a logic 0 must be written to this bit. clkout pin control (ocr01) this bit enables the clkout pin when set to 1 and, there- fore, outputs a 54 mhz clock generated by the internal pll. the pll and 4 oversampling have to be enabled for this con- trol to take effect, (mr61 = 0; mr16 = 1). reserved (ocr02?3) a logic 0 must be written to this bit. reserved (ocr04?6) a logic 1 must be written to these bits. reserved (ocr07) a logic 0 must be written to this bit.
ADV7192 C45C rev. 0 appendix 1 board design and layout considerations the ADV7192 is a highly integrated circuit containing both precision analog and high-speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high-speed digital circuitry. it is im perative that these same design and layout techniques be applied to the system level design such that high-speed, accurate p erformance is achieved. the recommended analog circuit layout shows the analog interface between the device and monitor. the layout should be optimized for lowest noise on the ADV7192 power and ground lines by shielding the digital inputs and pro- viding good decoupling. the lead length between groups of v aa and gnd pins should by minimized so as to minimize inductive ringing. ground planes the ground plane should encompass all ADV7192 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7192, the analog output traces, and all the digital signal traces leading up to the ADV7192. this should be as substantial as possible to maximize heat spreading and power dissipation on the board. power planes the ADV7192 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. t his bead should be located within three inches of the ADV7192. the metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all ADV7192 power pins and voltage reference cir cuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common-mode. supply decoupling for o ptimum performance, bypass capacit ors should be inst alled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is obtained with 0.1 f ceramic capacitor decoupling. each group of v aa pins on the ADV7192 must have at least one 0.1 f decoupling capacitor to gnd. these capacitors should be placed as close as possible to the device. it is important to note that while the ADV7192 contains cir cuitry to reject power supply noise, this rejection decreases with fre- quency. if a high frequency switching power supply is used, the designer should pay close attention to reduc ing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the ADV7192 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the ADV7192 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the ADV7192 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to imped ance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 300 ? load resistor connected to gnd. these resistors should be placed as close as possible to the ADV7192 so as to minimize reflections. the ADV7192 should have no inputs left floating. any inputs that are not required should be tied to ground.
ADV7192 C46C rev. 0 5v (v aa ) comp2 300 5k 5v (v aa ) 5k mpu bus 0.1 f 5v (v aa ) 4.7k 5v (v aa ) power supply decoupling for each power supply group 10 f agnd alsb hsync vsync blank reset clkin r set1 sdata scl dac a v aa v ref 5v (v dd ) screset/rtc/tr ADV7192 unused inputs should be grounded dac b 100 5v (v aa ) ttxreq 0.1 f comp1 vso /ttx/clamp pal_ntsc dac c dac d dac e dac f r set2 27mhz clock (same clock as used by mpeg2 decoder) cso_hso 4.7k 4.7 f 6.3v v dd 53, 48, 38 300 300 300 300 5v (v aa ) 100 1.2k 1.2k dgnd 52, 49, 35 80, 69, 43, 33, 22 79, 68, 34, 21 10 f 0.1 f 5v (v aa ) 0.1 f 300 cb0 C cb9 cr0 C cr9 y0/p8 C y7/p15 y8 C y9 p7 C p0 figure 95. recommended analog circuit layout
ADV7192 C47C rev. 0 appendix 2 closed captioning the ADV7192 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd elds and line 284 of even elds. closed captioning consists of a seven-cycle sinusoidal burst that is frequency and phase locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by a logic level 1 start bit. sixteen bits of data follow the start bit. these consist of two eight-bit bytes, seven data bits, and one odd parity bit. the data for these bytes is stored in closed captioning data registers 0 and 1. the ADV7192 also supports the extended closed captioning operation which is active during even elds and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. all clock run-in signals and timing to support closed captioning on lines 21 and 284 are generated automatically by the ADV7192 all pixels inputs are ignored during lines 21 and 284 if closed captioning is enabled. fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the ADV7192 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore, there will be no frame delay in outputting the closed captioning data unlike other two byte deep buffering systems. the data must be loaded one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, w hich in turn will load the new data (two bytes) every eld. if no new data is required for transmission, 0s must be inserted in both data registers, this is called nulling. it is also important to load control codes all of which are double bytes on line 21 or a tv will not recognize them. if there is a message like hello world which has an odd number of characters, it is important to pad it out to even in order to get end of caption 2-byte control code to land in the same eld. 12.91 s s t a r t p a r i t y p a r i t y d0Cd6 d0Cd6 10.003 s 33.764 s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 0.25 s two 7-bit + parity ascii characters (data) 27.382 s byte 0 byte 1 figure 96. closed captioning waveform (ntsc)
ADV7192 C48C rev. 0 appendix 3 copy generation management system (cgms) the ADV7192 supports copy generation management system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd elds and line 283 of even elds. bits c/w05 and c/w06 control whether or not cgms data is outputed on odd and even elds. cgms data can only be transmitted when the ADV7192 is con gured in ntsc mode. the cgms data is 20 bits long, the function of each of these bits is as shown below. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit, see figure 96. these bits are outputed from the con guration registers in the following order: c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/w11 = c9, c/w12 = c10, c/w13 = c11, c/w14 = c12, c/w15 = c 13, c/ w16 = c14, c/w17 = c15, c/w20 = c0, c/w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w25 = c5, c/w26 = c6, c/w27 = c7. if the bit c/w04 is set to a logic 1, the last six bits c19 c14 which comprise the 6-bit crc check sequence are calculated automatically on the ADV7192 based on the lower 14 bits (c0 c13) of the data in the data registers and output with the remaining 14-bits to form the complete 20-bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if c/w04 is set to a logic 0 then all 20-bits (c0 c19) are output directly from the cgms registers (no crc calcu- lated, must be calculated by the user). function of cgms bits word 0 6 bits word 1 4 bits word 2 6 bits crc 6 bits crc polynomial = x 6 + x + 1 (preset to 111111) word 0 1 0 b1 aspect ratio 16:9 4:3 b2 display format letterbox normal b3 unde ned word 0 b4, b5, b6 identi cation information about video and other signals (e.g., audio) word 1 b7, b8, b9, identi cation signal incidental to word 0 b10 word 2 b11, b12, identi cation signal and information b13, b14 incidental to word 0 crc sequence 49.1 s 0.5 s 11.2 s 2.235 s 20ns ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 100 ire 70 ire 0 ire C40 ire figure 97. cgms waveform diagram
ADV7192 C49C rev. 0 appendix 4 wide screen signaling the ADV7192 supports wide screen signaling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the ADV7192 is con gured in pal mode. the wss data is 14-bits long, the function of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code, see figure 97. the bits are output from the con guration registers in the following order: c/w20 = w0, c/w21 = w1, c/w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if the bit c/w07 is set to a l ogic 1, it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 s from the falling edge of hsync ) is available for the insertion of video. function of cgms bits bit 0 bit 2 aspect ratio/format/position bit 3 is odd parity check of bit 0 bit 2 aspect format position b0, b1, b2, b3 ratio format position 0 0 0 1 4:3 full format nonapplicable 1 0 0 0 14:9 letterbox center 0 1 0 0 14:9 letterbox top 1 1 0 1 16:9 letterbox center 0 0 1 0 16:9 letterbox top 1 0 1 1 >16:9 letterbox center 0 1 1 1 14:9 full format center 1 1 1 0 16:9 nonapplicable nonapplicable b4 0 camera mode 1 film mode b5 0 standard coding 1 motion adaptive color plus b6 0 no helper 1 modulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0 no surround sound information 1 surround sound mode b12 reserved b13 reserved w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 38.4 s 42.5 s 11.0 s figure 98. wss waveform diagram
ADV7192 C50C rev. 0 time, t pd , is the time needed by the ADV7192 to i nterpolate input data on ttx and insert it onto the cvbs or y outputs, such that it appears t syntxtout = 10.2 s after the leading edge of the horizontal signal. time txt del is the pipe line delay time by the source that is gated by the ttreq signal in order to de- liver ttx data. with the programmability that is offered with ttxreq signal on the rising/falling edges, the ttx data is always inserted at the correct position of 10.2 s after the leading edge of h orizontal sync pulse, thus this enables a source interface with variable pipeline delays. the width of the ttxreq signal must always be maintained such that it allows the insertion of 360 (in order to comply with the teletext standard pal-wst) teletext bits at a text data rate of 6.9375 mbits/s, this is achieved by setting tc03 tc00 to 0. the insertion window is not open if the teletext enable bit (mr34) is set to 0. appendix 5 teletext insertion teletext protocol the relationship between the ttx bit clock (6.9375 mhz) and the system clock (27 mhz) for 50 hz is given as follows: (27 mhz /4) = 6.75 mhz (6.9375 10 6 /6.75 10 6 = 1.027777 thus 37 ttx bits correspond to 144 clocks (27 mhz), each bit has a width of almost four clock cycles. the ADV7192 uses an internal sequencer and variable phase interpolation lter to mini- mize the phase jitter and thus generate a bandlimited signal which can be output on the cvbs and y outputs. at the ttx input the bit duration scheme repeats after every 37 ttx bits or 144 clock cycles. the protocol requires that ttx bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. after 37 ttx bits, the next bits with three clock cycles are bits 47, 56, 65, and 74. this scheme holds for all following cycles of 37 ttx bits, until all 360 ttx bits are completed. all teletext lines are implemented in the same way. individual control of teletext lines are controlled by teletext setup registers. address & data run-in clock teletext vbi line 45 bytes (360 bits) C pal figure 99. teletext vbi line programmable pulse edges t pd t pd cvbs/y hsync ttxreq ttx data t syntxtout = 10.2 s t pd = pipeline delay through ADV7192 ttx del = ttxreq to ttx (programmable range = 4 bits [0C15 clock cycles]) t syntxtout 10.2 s ttx del ttx st figure 100. teletext functionality diagram
ADV7192 C51C rev. 0 appendix 6 optional output filter if an output lter is required for the cvbs, y, uv, chroma and rgb outputs of the ADV7192, the following lter in fi gure 101 can be used in 2 oversampling mode. in 4 oversam pling mode the lter in figure 103 is recommended. the plot of the lter characteristics are shown in figures 102 and 104. an output 0.82 h 470pf 2.5 h filter i/p filter o/p figure 101. output filter for 2 oversampling mode 50 100k C100 C50 0 100m 1.0g C150 amplitude C db frequency C hz 1.0m 10m figure 102. output filter plot for 2 oversampling filter lter is not required if the outputs of the ADV7192 are con nected to most analog monitors or tvs, however, if the o utput signals are applied to a system where sampling is used, (e.g., digital tvs) then a lter is required to prevent aliasing. filter i/p filter o/p 470pf 2.2 h figure 103. output filter for 4 oversampling mode 20 100k C80 C40 C20 100m 1.0g C100 amplitude C db frequency C hz 1.0m 10m 0 C60 figure 104. output filter plot for 4 oversampling filter 27.0 40.5 54.0 13.5 6.75 frequency C mhz 2 filter requirements 4 filter requirements 0 C30 db figure 105. output filter requirements in 4 oversampling mode
ADV7192 C52C rev. 0 appendix 7 dac buffering external buffering is needed on the ADV7192 dac outputs. the con guration in figure 106 is recommended. when calculating absolute output full-scale current and voltage use the following equations: v out = i out r load i out = ( v ref k )/ r set k = 4.2146 constant , v ref = 1.235 v ADV7192 v ref pixel port v aa output buffer dac a cvbs chroma g luma b r 1.2k r set1 dac b dac c dac d dac e dac f digital core 1.2k r set2 output buffer output buffer output buffer output buffer output buffer figure 106. output dac buffering con?guration output to tv monitor input/ optional filter o/p +v cc ad8051 Cv cc 1 5 4 3 2 figure 107. recommended dac output buffer using an op amp
ADV7192 C53C rev. 0 appendix 8 recommended register values ntsc (f sc = 3.5795454 mhz) address data 00hex mode register 0 10hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 16hex 0dhex subcarrier frequency register 1 7chex 0ehex subcarrier frequency register 2 f0hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex pal b, d, g, h, i (f sc = 4.43361875 mhz) address data 00hex mode register 0 11hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr0 44hex 24hex dnr1 20hex 25hex dnr2 00hex 35hex output clock register 70hex the ADV7192 registers can be set depending on the user standard required. the following examples give the various register for- mats for several video standards.
ADV7192 C54C rev. 0 pal n (f sc = 4.43361875 mhz) address data 00hex mode register 0 13hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 4hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex pal 60 (f sc = 4.43361875 mhz) address data 00hex mode register 0 12hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex
ADV7192 C55C rev. 0 pal m (f sc = 3.57561149 mhz) address data 00hex mode register 0 12hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 a3hex 0dhex subcarrier frequency register 1 efhex ehex subcarrier frequency register 2 e6hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex address data 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex
ADV7192 C56C rev. 0 power-on reset reg values (pal_ntsc = 0, ntsc selected) address data 00hex mode register 0 00hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 00hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 16hex 0dhex subcarrier frequency register 1 7chex 0ehex subcarrier frequency register 2 f0hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 00hex 24hex dnr 1 00hex 25hex dnr 2 00hex 26hex gamma 0 xxhex 27hex gamma 1 xxhex 28hex gamma 2 xxhex 29hex gamma 3 xxhex 2ahex gamma 4 xxhex 2bhex gamma 5 xxhex 2chex gamma 6 xxhex 2dhex gamma 7 xxhex 2ehex gamma 8 xxhex 2fhex gamma 9 xxhex 30hex gamma 10 xxhex 31hex gamma 11 xxhex 32hex gamma 12 xxhex 33hex gamma 13 xxhex 34hex brightness detect register xxhex 35hex output clock register 72hex power-on reset reg values (pal_ntsc = 1, pal selected) address data 00hex mode register 0 01hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 00hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 00hex 24hex dnr 1 00hex 25hex dnr 2 00hex 26hex gamma 0 xxhex 27hex gamma 1 xxhex 28hex gamma 2 xxhex 29hex gamma 3 xxhex 2ahex gamma 4 xxhex 2bhex gamma 5 xxhex 2chex gamma 6 xxhex 2dhex gamma 7 xxhex 2ehex gamma 8 xxhex 2fhex gamma 9 xxhex 30hex gamma 10 xxhex 31hex gamma 11 xxhex 32hex gamma 12 xxhex 33hex gamma 13 xxhex 34hex brightness detect register xxhex 35hex output clock register 72hex power-on reset register values
ADV7192 C57C rev. 0 appendix 9 ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire C40 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 108. ntsc composite video levels 100 ire 7.5 ire 0 ire C40 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 109. ntsc luma video levels 650mv 232.2mv 1067.7mv 0mv peak chroma blank/black level 286mv (pk-pk) 835mv (pk-pk) peak chroma figure 110. ntsc chroma video levels 100 ire 7.5 ire 0 ire C40 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv figure 111. ntsc rgb video levels
ADV7192 C58C rev. 0 ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire C40 ire peak composite ref white sync level blank/black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv figure 112. ntsc composite video levels 100 ire 0 ire C40 ire ref white sync level blank/black level 714.2mv 1052.2mv 338mv 52.1mv figure 113. ntsc luma video levels 650mv 198.4mv 1101.6mv 0mv peak chroma blank/black level 307mv (pk-pk) peak chroma 903.2mv (pk-pk) figure 114. ntsc chroma video levels 100 ire 0 ire C40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv figure 115. ntsc rgb video levels
ADV7192 C59C rev. 0 pal waveforms 1284.2mv 1047.1mv 350.7mv 50.8mv peak composite ref white sync level blank/black level 696.4mv figure 116. pal composite video levels 1047mv 350.7mv 50.8mv ref white sync level blank/black level 696.4mv figure 117. pal luma video levels 650mv 207.5mv 1092.5mv 0mv peak chroma blank/black level 300mv (pk-pk) 885mv (pk-pk) peak chroma figure 118. pal chroma video levels 1050.2mv 351.8mv 51mv ref white sync level blank/black level 698.4mv figure 119. pal rgb video levels
ADV7192 C60C rev. 0 video measurement plots gray yellow cyan green magenta red blue black 0 50 100 luminance level (ire) 99.6 69.0 55.9 48.1 36.3 28.3 15.7 7.7 gray yellow cyan green magenta red blue black 0.0 62.1 87.6 81.8 81.8 87.8 62.1 0.0 chrominance level (ire) 0 50 100 gray yellow cyan green magenta red blue black 400 200 0 167.3 283.8 240.9 60.80 103.6 347.1 chrominance phase (degree) average 32 32 color bar (ntsc) field = 1 line = 21 wfm fcc color bar figure 120. ntsc color bar measurement gray yellow cyan green magenta red blue black 0 500 1000 luminance level (mv) 695.7 464.8 366.6 305.7 217.3 156.4 61.2 C0.4 gray yellow cyan green magenta red blue black 0 500 1000 0.0 474.4 669.1 623.5 624.7 669.6 475.2 0.0 chrominance level (mv) gray yellow cyan green magenta red blue black 400 200 0 100 300 166.7 283.3 240.4 60.4 103.2 346.7 chrominance phase (degree) average 32 32 color bar (pal) field = 1 line = 21 wfm fcc color bar figure 121. pal color bar measurement
ADV7192 C61C rev. 0 dg dp (ntsc) wfm field = 1, line = 21 mod 5 step 1 st C2.5 C1.5 C0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.21 0.02 0.07 0.27 0.08 diifferential gain (percent) min = 0.00, max = 0.27, p-p/max = 0.27 1 st C2.5 C1.5 C0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.10 0.12 0.15 0.13 0.10 differential phase (degree) min = 0.00, max = 0.20, p-p = 0.20 average 32 32 figure 122. ntsc dg dp measurement 89 91 93 95 97 99 101 103 105 107 109 111 1 st 2 nd 3 rd 4 th 5 th 99.9 99.9 99.6 100.0 99.9 average 32 32 luminance nonlinearity (ntsc) wfm field = 2, line = 77 luminance nonlinearity (percent) mod 5 step p-p = 0.4 figure 123. ntsc luminance nonlinearity 1 st C2.5 C1.5 C0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.09 0.13 0.16 0.12 0.14 differential phase (degree) min = 0.00, max = 0.16, p-p = 0.16 1 st C2.5 C1.5 C0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.30 0.15 0.24 0.32 0.26 diifferential gain (percent) min = 0.00, max = 0.32, p-p/max = 0.32 dg dp (pal) wfm line = 570 mod 5 step average 32 32 figure 124. pal dg dp measurement 91 93 95 97 99 101 103 105 107 109 111 113 1 st 2 nd 3 rd 4 th 5 th 99.6 99.9 100.0 99.6 99.9 average 32 32 luminance nonlinearity (pal) wfm line = 570 luminance nonlinearity (percent) p-p = 0.8 mod 5 step figure 125. pal luminance nonlinearity
ADV7192 C62C rev. 0 20ire C10 10 0 40ire 80ire 0.5 0.0 C0.3 chrominance amplitude error (percent) ref = 40ire packet 20ire C5 5 0 40ire 80ire C0.0 0.0 0.0 chrominance phase error (degree) ref = 40ire packet 20ire C0.1 0.2 0.1 40ire 80ire 0.0 0.1 0.1 0.0 C0.2 average 32 32 chrominance luminance intermodulation (percent of 714 mv) chrominance nonlinearity(ntsc) wfm ntscC7 combination field = 2, line = 217 figure 126. ntsc chrominance nonlinearity C95 C90 C85 C80 C75 C70 C65 C60 C95 C90 C85 C80 C75 C70 C65 C60 pm noise C82.7db rms am noise C86.5db rms ( 0db = 714mv p - p with agc for 100% chrominance level ) db rms db rms chrominance am/pm (ntsc) wfm red field field = 2, line = 217 bandwidth 10khz to 100khz figure 127. ntsc chrominance am/pm chrominance nonlinearity(pal) wfm mod 3 step line = 572 140mv C10 10 0 420mv 700mv 0.6 0.0 C0.4 chrominance amplitude error (percent) ref = 420mv packet 140mv C5 0 420mv 700mv C0.3 0.0 C0.3 chrominance phase error (degree) ref = 420mv packet 140mv 0.2 420mv 700mv 0.0 0.0 0.1 0.0 C0.2 average 32 32 chrominance luminance intermodulation (percent of 700mv) figure 128. pal chrominance nonlinearity C95 C90 C85 C80 C75 C70 C65 C60 C95 C90 C85 C80 C75 C70 C65 C60 pm noise C82.7db rms am noise C84.2db rms ( 0db = 700mv p - p with agc for 100% chrominance level ) db rms db rms chrominance am/pm (pal) wfm appropriate line = 572 bandwidth 10khz to 100khz figure 129. pal chrominance am/pm
ADV7192 C63C rev. 0 C100 C80 C60 C40 C20 0 20 noise spectrum (ntsc) wfm field = 2, line = 223 amplitude (0db = 714mv p-p) 1234 56 mhz bandwidth 10khz to full pedestal noise level = C79.7db rms figure 130. ntsc noise spectrum: pedestal C100 C90 C80 C50 C40 C20 0 noise spectrum (ntsc) wfm field = 2, line = 217 amplitude (0db = 714mv p-p) 1234 56 mhz bandwidth 100khz to full (tilt null) C70 C60 C30 C10 ramp noise level = C63.1db rms figure 131. ntsc noise spectrum: ramp C100 C80 C60 C40 C20 0 noise spectrum (pal) wfm line = 511 amplitude (0db = 714mv p-p) 123 4 57 mhz bandwidth 10khz to full 6 pedestal noise level = C79.1db rms figure 132. pal noise spectrum: pedestal C100 C90 C80 C50 C40 C20 0 noise spectrum (pal) wfm line = 572 amplitude (0db = 700mv pCp) 123 4 5 7 mhz bandwidth 100khz to full (tilt null) C70 C60 C30 C10 6 noise level = C62.3db rms ramp figure 133. pal noise spectrum: ramp
ADV7192 C64C rev. 0 betacam level 0mv 171mv 334mv 505mv 0mv 171mv 334mv 505mv white yellow cyan green magenta red blue black figure 134. ntsc 100% color bars no pedestal u levels betacam level 0mv 158mv 309mv 467mv 0mv C158mv C309mv C467mv white yellow cyan green magenta red blue black figure 135. ntsc 100% color bars with pedestal u levels smpte level 0mv 118mv 232mv 350mv 0mv C118mv C232mv C350mv white yellow cyan green magenta red blue black figure 136. pal 100% color bars u levels uv waveforms betacam level 0mv 82mv 423mv 505mv 0mv C82mv C505mv C423mv white yellow cyan green magenta red blue black figure 137. ntsc 100% color bars no pedestal v levels betacam level 0mv 76mv 391mv 467mv 0mv C76mv C467mv C391mv white yellow cyan green magenta red blue black figure 138. ntsc 100% color bars with pedestal v smpte level 0mv 57mv 293mv 350mv 0mv C57mv C350mv C293mv white yellow cyan green magenta red blue black figure 139. pal 100% color bars v levels
ADV7192 C65C rev. 0 0.6 0.4 0.2 0.0 0.2 l608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 microseconds noise reduction: 0.00 db apl = 39.1% precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 3 4 volts figure 140. 100%/75% pal color bars microseconds apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 l575 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 volts no bruch signal figure 141. 100%/75% pal color bars luminance output waveforms
ADV7192 C66C rev. 0 apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 C0.5 10.0 30.0 40.0 50.0 60.0 20.0 microseconds l575 volts no bruch signal figure 142. 100%/75% pal color bars chrominance apl = 44.6% precision mode off 525 line ntsc no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.5 0.0 C50.0 50.0 100.0 ire:flt volts f1 l76 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.0 figure 143. 100%/75% ntsc color bars
ADV7192 C67C rev. 0 noise reduction: 15.05db apl = 44.7% precision mode off 525 line ntsc no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 10.0 20.0 30.0 40.0 50.0 60.0 0.6 0.4 0.2 0.0 C0.2 50.0 0.0 ire:flt volts f2 l238 100.0 figure 144. 100%/75% ntsc color bars luminance noise reduction: 15.05db apl needs sync = source! precision mode off 525 line ntsc no filtering synchronous sync = b slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.4 0.2 0.0 C0.2 C0.4 volts 50.0 C50.0 f1 l76 ire:flt figure 145. ntsc color bars chrominance
ADV7192 C68C rev. 0 appendix 10 vector plots apl = 39.6% sound in sync off v u yi yl g r m g cy m g cy g r 75% 100% b b system line l608 angle (deg) 0.0 gain 1.000 0.000db 625 line pal burst from source display +v and Cv figure 146. pal vector plot apl = 45.1% setup 7.5% r-y b-y yi g cy m g cy i r 75% 100% b b system line l76f1 angle (deg) 0.0 gain 1.000 0.000db 525 line ntsc burst from source q Cq Ci figure 147. ntsc vector plot
ADV7192 C69C rev. 0 outline dimensions dimensions shown in inches and (mm). 80-lead lqfp (st-80) top view (pins down) 1 20 21 41 40 60 61 80 0.640 (16.25) 0.620 (15.75) sq 0.553 (14.05) 0.549 (13.95) sq 0.014 (0.35) 0.010 (0.25) 0.029 (0.73) 0.022 (0.57) 0.486 (12.35) typ sq 0.063 (1.60) max 0.030 (0.75) 0.020 (0.50) seating plane 0.006 (0.15) 0.002 (0.05) 0.004 (0.10) max 0.057 (1.45) 0.053 (1.35) c3748C8C4/00 (rev. 0) 00229 printed in u.s.a.

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